74LVC821ABQ Datasheet, PDF (1/20 Pages) List of Unclassifed Manufacturers – 10-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive-edge trigger; 3-state

74LVC821A
10-bit D-type flip-flop with 5 V tolerant inputs/outputs;
positive-edge trigger; 3-state
Rev. 03 — 11 May 2004
Product data sheet
1. General description
The 74LVC821A is a high performance, low power, low voltage Si-gate CMOS device and
superior to most advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices. In 3-state operation, outputs can
handle 5 V. This feature allows the use of these devices as translators in a mixed 3.3 V
and 5 V environment.
The 74LVC821A is a 10-bit D-type flip-flop featuring separate D-type inputs for each
flip-flop and 3-state outputs for bus-oriented applications. A clock input (pin CP) and an
output enable input (pin OE) are common to all flip-flops. The ten flip-flops will store the
state of their individual D-inputs that meet the set-up and hold times requirements on the
LOW-to-HIGH CP transition. When pin OE is LOW, the contents of the ten flip-flops is
available at the outputs.
When pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the
OE inputs does not affect the state of the flip-flops.
2. Features
s 5 V tolerant inputs and outputs; for interfacing with 5 V logic
s Wide supply voltage range from 1.2 V to 3.6 V
s Inputs accept voltages up to 5.5 V
s CMOS low power consumption
s Direct interface with TTL levels
s Flow-through pin-out architecture
s 10-bit positive edge-triggered register
s Independent register and 3-state buffer operation
s Complies with JEDEC standard JESD8-B
s ESD protection:
x HBM EIA/JESD22-A114-B exceeds 2000 V
x MM EIA/JESD22-A115-A exceeds 200 V.
s Specified from −40 °C to +85 °C and −40 °C to +125 °C.