22CV10AZ-25 Datasheet, PDF (1/10 Pages) List of Unclassifed Manufacturers – CMOS Programmable Electrically Erasable Logic Device

Commercial/
Industrial
PEEL™ 22CV10AZ -25
CMOS Programmable Electrically Erasable Logic Device
Features
s Ultra Low Power Operation
- VCC = 5 Volts ±10%
- Icc = 10 µA (typical) at standby
- Icc = 2 mA (typical) at 1 MHz
- tPD = 25ns.
s CMOS Electrically Erasable Technology
- Superior factory testing
- Reprogrammable in plastic package
- Reduces retrofit and development costs
s Development/Programmer Support
- Third party software and programmers
- ICT PLACE Development Software and PDS-3
programmer
s Architectural Flexibility
- 133 product terms x 44 input AND array
- Up to 22 inputs and 10 I/O pins
- 12 possible macrocell configurations
- Synchronous preset, asynchronous clear
- Independent output enables
- Programmable clock source and polarity
- 24-pin DIP/SOIC/TSSOP and 28-pin PLCC
s Application Versatility
- Replaces random logic
- Pin and JEDEC compatible with 22V10
- Ideal for power-sensitive systems
General Description
The PEEL™22CV10AZ is a Programmable Electrically
Erasable Logic (PEEL™) device that provides a low power
alternative to ordinary PLDs. The PEEL™22CV10AZ is
available in 24-pin DIP, SOIC, TSSOP and 28-pin PLCC
packages (see Figure 19).
A “zero-power” (100µA max. ICC) standby mode makes the
PEEL™22CV10AZ ideal for power sensitive applications
such as handheld meters, portable communication equip-
ment and laptop computers/ peripherals. EE-reprogramma-
bility provides the convenience of instant reprogramming
for development and a reusable production inventory mini-
mizing the impact of programming changes or errors. EE-
reprogrammability also improves factory testability, thus
ensuring the highest quality possible.
The PEEL™22CV10AZ is JEDEC file compatible with stan-
dard 22V10 PLDs. Eight additional configurations per mac-
rocell (a total of 12) are also available by using the “+”
software/programming option (i.e., 22CV10AZ+). The addi-
tional macrocell configurations allow more logic to be put
into every device, potentially reducing the design's compo-
nent count and lowering the power requirements even fur-
ther.
Development and programming support for the
PEEL™22CV10AZ is provided by popular third-party pro-
grammers and development software. ICT also offers free
PLACE development software and a low-cost development
system (PDS-3).
Figure 19 Pin Configuration
DIP
I/CLK
1
I
2
I
3
I
4
I
5
I
6
I
7
I
8
I
9
I
10
I
11
GND
12
TSSOP
24
VCC
23
I/O
22
I/O
21
I/O
20
I/O
19
I/O
18
I/O
17
I/O
16
I/O
15
I/O
14
I/O
13
I
Figure 19 Block Diagram
PLCC
SOIC
1 of 10