SQ930C Datasheet, PDF (9/20 Pages) List of Unclassifed Manufacturers – High-Speed USB 2.0 Video Camera Controller

SQ930C
High-Speed USB 2.0 Video Camera Controller
2.2.3 LFBGA 64 Pin Descriptions
PIN NO
C3
D2
C4
D3
C5
D5
B5
D6
C6
D4
F4
E5
B6
E4
B3
B4
NAME
AGND2
AVCC2
AGND3
AVCC3
VCCIO
GND
VCCK
GND
VCCIO
ZREGO3.3
ZREGO2.5
GND
VCCK
GND
AVCC1
AGND1
TABLE 2–2: POWER SUPPLY PINS (LFBGA 64)
I/O
DESCRIPTION
PWR
Analog ground
PWR
PWR
Power, Analog AVCC=3.3
Analog ground
PWR
PWR
PWR
Power, Analog AVCC=3.3
Power, Digital VCC=3.3
Digital ground
PWR
Power, Digital VCCK=2.5
PWR
Digital ground
PWR
Power, Digital VCC=3.3
PWR
Power, Digital VCC=3.3
PWR
Power, Digital VCCK=2.5
PWR
Digital ground
PWR
Power, Digital VCCK=2.5
PWR
Digital ground
PWR
Analog AVCC=3.3
PWR
Analog ground
PIN NO
A6
A4
A3
NAME
NRES
XOSCI
XOSCO
TABLE 2–3: SYSTEM PINS (LFBGA 64)
I/O
DESCRIPTION
I
Digital input Pull high to force ASIC normal action, low will into reset state.
I
12M Crystal in
O
12M Crystal out
PIN NO
NAME
D1
CPU_P3.1
E3, E1, F1, E2, CPU_P2.6~
F2, G1, H1
CPU_P2.0
H2
CPU_PSEN
G2, F3, H3, G3 CPU_P1.3~
CPU_P1.0
H4, G4, G5, H5, CPU_P0.7~
F5, G6, H6, H7 CPU_P0.0
H8
CPU_ALE
TABLE 2–4: 8032 CPU INTERFACE PINS (LFBGA 64)
I/O
DESCRIPTION
I/O
Port 3.1 bi-directional I/O port
O
Microprocessor High Address Bus
O
Program Store Enable is the read strobe to external program memory.
I/O
Port 1.3~ Port 1.0 is an 4-bit bi-directional I/O port
I/O
Microprocessor Data / Low Address Bus
O
Address Latch Enable output pulse for latching the low byte of the address
during accesses to external memory.
Subject to Change Without Notice.
PAGE 9
Version 1.3 - April 22^nd , 2005