SPT7937 Datasheet, PDF (8/11 Pages) List of Unclassifed Manufacturers – 12-BIT, 28 MSPS, 170 mW A/D CONVERTER

Figure 4 – Simplified Reference Ladder Drive Circuit
Without Force/Sense Circuit
+4.0 V
External
Reference
V_RHS
(+3.91 V)
21 mV R/2
R
R
V_RLS
(0.075 V)
V_RLF (AGND)
0.0 V
R
R
R
R
50 mV R/2
R=30 Ω (typ)
All capacitors are 0.01 µF
In cases in which wider variations in offset and gain can be
tolerated, V_Ref can be tied directly to V_RHF and AGND can
be tied directly to V_RLF as shown in figure 4. Decouple force
and sense lines to AGND with a 0.01 µF capacitor (chip cap
preferred) to minimize high-frequency noise injection. If this
simplified configuration is used, the following considerations
should be taken into account:
The reference ladder circuit shown in figure 4 is a simplified
representation of the actual reference ladder with force and
sense taps shown. Due to the actual internal structure of the
ladder, the voltage drop from V_RHF to V_RHS is not equivalent
to the voltage drop from V_RLF to V_RLS.
Typically, the top side voltage drop for V_RHF to V_RHS will
equal:
V_RHF – V_RHS = 0.5% of (V_RHF – V_RLF) (typical),
and the bottom side voltage drop for V_RLS to V_RLF will equal:
V_RLS – V_RLF = 1.25% of (V_RHF – V_RLF) (typical).
Figure 4 shows an example of expected voltage drops for a
specific case. V_REF of 4.0 V is applied to V_RHF and V_RLF is
tied to AGND. A 21 mV drop is seen at V_RHS (= 3.79 V) and
a 50 mV increase is seen at V_RLS (= 0.050 V).
ANALOG INPUT
V_IN is the analog input. The input voltage range is from V_RLS
to V_RHS (typically 4.0 V) and will scale proportionally with re-
spect to the voltage reference. (See the Voltage Reference
section.)
The drive requirements for the analog inputs are very mini-
mal when compared to most other converters due to the
SPT7937’s extremely low input capacitance of only 5 pF
and very high input resistance in excess of 35 kΩ.
The analog input should be protected through a series resis-
tor and diode clamping circuit as shown in figure 5. To pre-
vent possible latch-up condition, the power supplies must
be powered up before the input is applied.
Figure 5 – Recommended Input Protection Circuit
+V
AV_DD
Buffer
D1
47 Ω
D2
ADC
–V
D1 = D2 = Hewlett Packard HP5712 or equivalent
CALIBRATION
The SPT7937 uses a user-transparent, auto-calibration
scheme to ensure 12-bit accuracy over time and tempera-
ture. Gain and offset errors are continually adjusted to 12-bit
accuracy during device operation.
Upon power up, the SPT7937 begins its calibration algo-
rithm. In order to achieve the calibration accuracy required,
the offset and gain adjustment step size is a fraction of a 12-
bit LSB. Since the calibration algorithm is an oversampling
process, a minimum of 10,000 clock cycles are required.
This results in a minimum calibration time upon power-up of
357 µsec (for a 28 MHz clock). Once calibrated, the
SPT7937 remains calibrated over time and temperature.
Since the calibration cycles are initiated on the rising edge
of the clock, the clock must be continuously applied for the
SPT7937 to remain in calibration.
SPT
8
SPT7937
1/14/00