GS82032T Datasheet, PDF (8/23 Pages) List of Unclassifed Manufacturers – 64K x 32 2M Synchronous Burst SRAM

Preliminary
GS82032T/Q-150/138/133/117/100/66
Simplified State Diagram with G
X
Deselect
W
R
W
R
X
First Write ^R
CW
CR
W
First Read
X
CW
CR
W
X
R
Burst Write
CR
CW
R
W _{Burst Read X}
CW
CR
Notes:
1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passing
through a deselect cycle. Dummy read cycles increment the address counter just like normal read cycles.
3. Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
Data Input Set Up Time.
Rev: 1.04 2/2001
8/23
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.