PDM41028 Datasheet, PDF (7/8 Pages) List of Unclassifed Manufacturers – 1 Megabit Static RAM 256K x 4-Bit

PDM41028
AC Electrical Characteristics
Description
WRITE Cycle
-10⁽⁷⁾
-12⁽⁷⁾
-15
1
Sym Min. Max. Min. Max. Min. Max. Units
WRITE Cycle time
t_WC
10
12
15
ns
Chip enable active time
t_CW
10
10
11
ns
2
Address Valid to end of write
t_AW
10
10
11
ns
Address setup time
t_AS
0
0
0
ns
Address hold from end of write
t_AH
0
0
0
ns
Write pulse width
t_WP1
9
10
11
ns
3
Write pulse width
t_WP2
10
11
12
ns
Data setup time
Data hold time
t_DS
7
7
7
ns
t_DH
0
0
0
ns
4
Write disable to output in low Z^(1,3)
t_LZWE
0
0
0
ns
Write enable to output in high Z^(1,3) t_HZWE
7
7
7 ns
SHADED AREA = PRELIMINARY DATA
5
Notes referenced are after Data Retention Table
Low V_CC Data Retention Waveform
6
Data Retention Mode
V _CC
4.5V
VDR
4.5V
7
t _CDR
t_R
VIH
CE _VIL
VDR
8
DON'T CARE
Data Retention Electrical Characteristics (LA Version Only)
9
Symbol Parameter
Test Conditions
Min. Typ. Max. Unit
V_DR
I_CCDR
VCC for Retention Data
Data Retention Current
CE ≥ V_CC – 0.2V
V_IN ≥ V_CC – 0.2V
or ≤ 0.2V
2
V_CC = 2V
—
V_CC = 3V
—
—
—
10 ^—
V
500 µA
—
750 µA
t_CDR
t_R(3)
Chip Deselect to Data Retention Time
Operation Recovery Time
0
t_RC
—
—
11 ^—
ns
—
ns
NOTES: (For three previous Electrical Characteristics tables)
1. The parameter is tested with CL = 5 pF as shown in Figure 2. Transition is measured ±200 mV from steady state voltage.
2. At any given temperature and voltage condition, t_HZCE is less than t_LZCE.
3. This parameter is sampled.
4. WE is high for a READ cycle.
12
5. The device is continuously selected. Chip Enable is held in its active state.
6. The address is valid prior to or coincident with the latest occuring Chip Enable.
7. Vcc = 5V ± 5%.
Rev. 2.2 - 4/29/98
7