PDM31096 Datasheet, PDF (7/8 Pages) List of Unclassifed Manufacturers – 4 Megabit 3.3V Static RAM 512K x 8-Bit

PRELIMINARY
PDM31096
Write Cycle No. 3 (Chip Enable Controlled)
tWC
1
ADDR
tAW
tAH
tAS
tCW
2
CE
tWP
3
WE
tDS
tDH
DIN
DATA VALID
4
DOUT
HIGH-Z
NOTE: Output Enable (OE) is inactive (high)
5
6
AC Electrical Characteristics
Description
WRITE Cycle
-8*
-10*
-12
-15
-20
7
Sym Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
WRITE cycle time
Chip enable to end of write
Address valid to end of write
t_WC
8 — 10 — 12 — 15 — 20 — ns
t_CW
8 — 10 — 10 — 11 — 13 — ns
t_AW
8 — 10 — 10 — 11 — 13 — ns
Address setup time
Address hold from end of write
Write pulse width
t_AS
0 — 0 — 0 — 0 — 0 — ns
t_AH
0 — 0 — 0 — 0 — 0 — ns
t_WP
7 — 8 — 8 — 9 — 10 — ns
Data setup time
t_DS
5 — 6 — 7 — 8 — 9 — ns
Data hold time
t_DH
0 — 0 — 0 — 0 — 0 — ns
Write disable to output in low Z^(1,3)
t_LZWE
0
—
0
—
0
—
0—
0
— ns
Write enable to output in high Z^(1,3)
t_HZWE —
4
5 — 6 — 7 — 9 ns
8
9
10
* V_CC = 3.3V +5%
NOTES: (For two previous Electrical Characteristics tables)
1. The parameter is tested with CL = 5 pF as shown in Figure 2. Transition is measured ±200 mV from steady state voltage.
2. At any given temperature and voltage condition, t_HZCE is less than t_LZCE.
3. This parameter is sampled.
4. WE is high for a READ cycle.
5. The device is continuously selected. All the Chip Enables are held in their active state.
6. The address is valid prior to or coincident with the latest occuring Chip Enable.
11
12
Rev. 2.4 - 5/27/98
7