NT3883 Datasheet, PDF (7/12 Pages) List of Unclassifed Manufacturers – Dot Matrix LCD 80-Channel Driver

NT3883
Functional Description
NT3883 is a dot matrix LCD segment driver LSI. It
operates with the controller, such as NT3881B/C/D,
and/or another segment driver LSI NT3882A/3883.
NT3883 receives serial data from the controller or
another NT3883, converts it to parallel data and then
supplies the LCD driving waveforms to the LCD panel.
1. CL1
This signal is used for latching the shift register contents.
When CL1 is set at high, the shift register contents are
transferred to the 80-bit 4level LCD driver. When CL1 is
set at low, the last display output data (S1 to S80) is
held.
2. CL2
Clock pulse inputs for the two 40-bit shift registers. The
data is shifted to an 80-bit latch at the falling edge of
CL2. The clock signal CL2 must be active when
operating to refresh shift registers' contents.
3. DL1
Data input/output of the 1^st - 40^th register. When SL1 is
connected to GND or open, the data from LCD controller
is fed into the 1^st - 40^th register through DL1 serially. If
SL1 is connected to VDD, the DL1 becomes the output of
the 1^st - 40^th register.
4. DR1
Data input/output of the 1^st - 40^th register. When SL1 is
connected to GND, the 20^th bit of the 1^st - 40^th register
output from DR1. By connecting DR1 to DL2, two 40-bit
shift registers cascaded to one 80-bit shift register. If
SL1 is connected to VDD, the DR1 becomes the input of
the 1^st - 40^th register, in this case, the data may come
from DL2.
5. DL2
Data input/output of the 41^st - 80^th register. When SL2 is
connected to GND, the data from LCD controller is fed
into the 41^st - 80^th register through DL2 serially. If SL2 is
connected to VDD, the DL2 becomes the output of the
41^st - 80^th register.
6. DR2
Data input/output of the 41^st - 80^th register. When SL2 is
connected to GND, the 80^th bit of the 41^st - 80^th register
output from DR2. By connecting DR2 to DL1 of next
NT3882A/3883, the cascade structure is obtained to
drive a wider LCD panel. If SL2 is connected to VDD, the
DR2 becomes the input of the 41^st - 80^th register, in this
case, the data may come from the next NT3882A/3883.
7. SL1
The shift direction of S1 to S40, i.e. 1^st to 40^th shift
register, is selected by SL1. The detail function
description is listed in Note*4 of Page5.
8. SL2
The shift direction of S41 to S80, i.e. 41^st to 80^th shift
register, is selected by SL2. The detail function
description is listed in Note*4 of Page5.
9. S1 to S80
LCD driver output pins. These 80 bits represent the 80
data bits in the 80-bit latch and one of VDD, V2, V3 and
VEE is selected as a LCD driving voltage source
according to the combination of latched data level and
the alternate signal (M). The truth table is listed as
follows:
Latched Data
1(High)
(Selected)
0(Low)
(Non-selected)
M
1(High)
0(Low)
1(High)
0(Low)
Output Level of S1 to S80
VEE
VDD
V3
V2
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