A54SX08A Datasheet, PDF (66/108 Pages) List of Unclassifed Manufacturers – SX-A Family FPGAs

SX-A Family FPGAs
Table 2-37 • A54SX72A Timing Characteristics
(Worst-Case Commercial Conditions V_CCA = 2.25 V, V_CCI = 3.0 V, T_J = 70°C)
–3 Speed –2 Speed –1 Speed
Std. Speed
–F Speed
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Dedicated (Hardwired) Array Clock Networks
t_HCKH
Input Low to High
(Pad to R-cell Input)
1.6
1.9
2.1
2.5
3.8 ns
t_HCKL
Input High to Low
(Pad to R-cell Input)
1.7
1.9
2.1
2.5
3.8 ns
t_HPWH
Minimum Pulse Width High
t_HPWL
Minimum Pulse Width Low
t_HCKSW
Maximum Skew
t_HP
Minimum Period
f_HMAX
Maximum Frequency
Routed Array Clock Networks
1.5
1.7
2.0
2.3
3.2
ns
1.5
1.7
2.0
2.3
3.2
ns
1.4
1.6
1.8
2.1
3.3 ns
3.0
3.4
4.0
4.6
6.4
ns
333
294
250
217
156 MHz
t_RCKH
Input Low to High (Light Load)
(Pad to R-cell Input)
2.2
2.6
2.9
3.4
4.8 ns
t_RCKL
Input High to Low (Light Load)
(Pad to R-cell Input)
2.8
3.3
3.7
4.3
6.0 ns
t_RCKH
Input Low to High (50% Load)
(Pad to R-cell Input)
2.4
2.8
3.2
3.7
5.2 ns
t_RCKL
Input High to Low (50% Load)
(Pad to R-cell Input)
2.9
3.4
3.8
4.5
6.2 ns
t_RCKH
Input Low to High (100% Load)
(Pad to R-cell Input)
2.6
3.0
3.4
4.0
5.6 ns
t_RCKL
Input High to Low (100% Load)
(Pad to R-cell Input)
3.1
3.6
4.1
4.8
6.7 ns
t_RPWH
Minimum Pulse Width High
t_RPWL
Minimum Pulse Width Low
t_RCKSW
Maximum Skew (Light Load)
t_RCKSW
Maximum Skew (50% Load)
t_RCKSW
Maximum Skew (100% Load)
Quadrant Array Clock Networks
1.5
1.7
2.0
2.3
3.2
ns
1.5
1.7
2.0
2.3
3.2
ns
1.9
2.2
2.5
3
4.1 ns
1.9
2.1
2.4
2.8
3.9 ns
1.9
2.1
2.4
2.8
3.9 ns
t_QCKH
Input Low to High (Light Load)
(Pad to R-cell Input)
1.3
1.5
1.7
1.9
2.7 ns
t_QCHKL
Input High to Low (Light Load)
(Pad to R-cell Input)
1.3
1.5
1.7
2
2.8 ns
t_QCKH
Input Low to High (50% Load)
(Pad to R-cell Input)
1.5
1.7
1.9
2.2
3.1 ns
t_QCHKL
Input High to Low (50% Load)
(Pad to R-cell Input)
1.5
1.8
2
2.3
3.2 ns
t_QCKH
Input Low to High (100% Load)
(Pad to R-cell Input)
1.7
1.9
2.2
2.5
3.5 ns
2-46
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