STC809 Datasheet, PDF (6/13 Pages) List of Unclassifed Manufacturers – UP Supervisor Circuits

Data Sheet
STC803/809/810-811/812/-823/824/825-6342/6343/6344/6345
µP Supervisor Circuits
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Pin Description
Table 2. Pin Description
Pin Name Type
Descr iption
Manual-Reset: (CMOS). Active low. Pull low to force a reset. Reset remains asserted for the duration
MR
I of the Reset Timeout Period after MR transitions from low to high. Leave unconnected or connected
to VCC if not used.
Vcc
GND
Power
Ground
Power Supply: Reset is asserted when V_CC drops below the Reset Threshold Voltage (V_RST). Reset
remains asserted until V_CC rises above V_RST and keep asserted for the duration of the Reset Timeout
Period (t_RS) once V_CC rises above V_RST.
Ground Reference for all signals
PFI
I
Power-Fail Voltage Monitor Input. When PFI <V_PFT , PFO goes low. Connect PFI to GND or Vcc
when not used.
PFO
O
Power-Fail Output: it gets low and sinks current when PFI is less than 1.25V; otherwise PFO stays
high.
Watchdog Input (CMOS). If WDI remains high or low for the duration of the watchdog timeout period
WDI
I
(t ), the internal watchdog timer trigger a reset output. Floating WDI or connecting WDI to a high-
WD
impedance three-state buffer disables the watchdog feature. The internal watchdog timer clears
whenever reset is asserted or WDI occurs a rising or falling edge.
RESET
RESET
Active-Low Reset Output (Push-Pull or Open-Drain). It goes low when Vcc is below the reset
O threshold. It remains low for about 200ms after one of the following occurs: Vcc rises above the reset
threshold (V_RST), the watchdog triggers a reset, or MR goes from low to high.
O The inverse of RESET, active high. Whenever RESET is high, RESET is low.
NC
- No connection
STC
6
Ver1.0