KVR533D2S8F4 Datasheet, PDF (6/7 Pages) List of Unclassifed Manufacturers – Memory Module Specifications (512MB 64M x 72-BIT PC2-4200 CL4 ECC 240-Pin FBDIMM)

TECHNOLOGY
Advanced Memory Buffer Pin Description:
SCL
SDA
SA[2:0]
PLLTSTO
VCCAPLL
VSSAPLL
TEST_pin#
TESTLO_pin#
BFUNC
RESET
NC
RFU
SPD Bus Interface Signals
5
Serial Presence Detect (SPD) Clock Input
1
SPD Data Input / Output
1
SPD Address Inputs, also used to select the DIMM number in the AMB
3
Miscellaneous Signals
163
PLL Clock Observability Output
1
Analog VCC for the PLL. Tied with low pass filter to VCC.
1
Analog VSS for the PLL. Tied to ground on the AMB die. Do not tie to ground on the DIMM.
1
Leave floating on the DIMM
6
Tie to ground on the DIMM²
5
Tie to ground to set functionality as “buffer on DIMM.”
1
AMB reset signal
1
No connect. Many NC are connected to VDD on the DIMM, to lower the impedance of the VDD power
islands.
129
Reserved for Future Use
18
Power/Ground Signals
213
V_CC
V_CCFBD
V_DD
V_DDSPD
V_SS
AMB Core Power (1.5 Volt)
AMB Channel I/O Power (1.5 Volt)
AMB DRAM I/O Power (1.8 Volt)
SPD Power (3.3 Volt)
Ground
Total
24
8
24
1
156
655
1. System Clock Signals SCK and SCK switch at one half the DRAM CK/CK frequency.
2. TESTLO_AB20 and TESTLO_AC20 should be configured for debug purposes on prototype DIMMs: each pin should have a zero
ohm resistor pulldown to ground, and an unpopulated resistor pullup to VCC. These resistors can be replaced on production
DIMMs with a direct connection to ground.
VALUERAM0502-001.A00
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