RTL8101L Datasheet, PDF (53/68 Pages) List of Unclassifed Manufacturers – REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER AND MC97 CONTROLLER WITH POWER MANAGEMENT

RTL8101L
When the RTL8101L is in power down mode, ex. D1-D3, the IO, MEM, and Boot ROM space are all disabled. After RST#
asserted, the power state must be changed to D0 if the original power state is D3_cold. There is no hardware enforced delays at
RTL8101L’s power state. When in ACPI mode, the RTL8101L does not support PME from D0 (owing to the setting of PMC
register. This setting comes from EEPROM).
The RTL8101L also supports the LAN WAKE-UP function. The LWAKE pin is used to notify the motherboard to execute the
wake-up process whenever the RTL8101L receives a wakeup event, such as Magic Packet.
The LWAKE signal is asserted according the following setting:
LWPME bit (bit4, CONFIG4):
0: The LWAKE is asserted whenever there is wakeup event occurs.
1: The LWAKE can only be asserted when the PMEB is asserted and the ISOLATEB is low.
Bit1 of DELAY byte(offset 1Fh, EEPROM):
0: LWAKE signal is disabled.
1: LWAKE signal is enabled
8.5 VPD (Vital Product Data)
Bit 31 of the VPD is used to issue VPD read/write commands and is also a flag used to indicate whether the transfer of data
between the VPD data register and the 93C46 is completed or not.
1. Write VPD register: (write data to 93C46)
Write the flag bit to a one at the same time the VPD address is written. When the flag bit is set to zero by the RTL8101L, the
VPD data (all 4 bytes) has been transferred from the VPD data register to the 93C46.
2. Read VPD register: (read data from 93C46)
Write the flag bit to a zero at the same time the VPD address is written. When the flag bit is set to one by the RTL8101L, the
VPD data (all 4 bytes) has been transferred from 93C46 to the VPD data register.
2003-05-28
53
Rev.1.3