VMX1C1020 Datasheet, PDF (52/80 Pages) List of Unclassifed Manufacturers – Versa Mix 8051 Mixed-Signal MCU

VMX51C1020
I²C Interface
The VMX51C1020 includes an I²C compatible
communication interface that can be configured
in Master mode or in Slave mode.
I²C Control Registers
The I2CRXTX SFR register is used to retrieve
and transmit data on the I²C interface.
TABLE86: (I2CRXTX) I2C DATA BUFFER - SFR DEH
7
6
5
4
3
2
1
0
I2CRXTX [7:0]
Bit Mnemonic
Function
7:0
I2CRXTX[7:0]
I2C Data Receiver / Transmitter
buffer
The I2CCONFIG register serves to configure the
operation of the VMX51C1020 I²C interface.
The following table describes the I2CCONFIG
register bits.
TABLE 87: (I2CCONFIG) I2C CONFIGURATION - SFR DAH
7
6
5
I2CMASKID I2CRXOVIE I2CRXDAVIE
4
I2CTXEMPIE
3
I2CMANACK
2
I2CACKMODE
1
I2CMSTOP
0
I2CMASTER
Bit Mnemonic
Function
7
This is used to mask the chip ID
when you have only two devices.
I2CMASKID
Therefore in a transaction, rather
that receiving the chip ID first,
you will receive the first packet of
data.
6
I2CRXOVIE
I2C Receiver overrun interrupt
enable
5 I2CRXDAVIE I2C Receiver available interrupt
enable
4 I2CTXEMPIE I2C Transmitter empty interrupt
enable
3 I2CMANACK 1= Manual acknowledge line
goes to 0
0= Manual acknowledge line
goes to 1
2 I2CACKMODE Used only with Master Rx, Master
Tx, and Slave Rx.
1= Manual Acknowledge on
0= Manual Acknowledge off
1 I2CMSTOP
I2C Master receiver stops at next
acknowledge phase. (read during
data phase)
0 I2CMASTER I2C Master mode enable
1= I2C interface is Master
0= I2C interface is Slave
The I2CIRQSTAT register provides the status of
the I²C interface operation and monitors the I²C
bus status.
TABLE 88: (I2CIRQSTAT) I2C INTERRUPT STATUS - SFR DDH
7
6
5
I2CGOTSTOP I2CNOACK I2CSDA
4
I2CDATACK
3
I2CIDLE
2
I2CRXOV
1
I2CRXAV
0
I2CTXEMP
Bit
Mnemonic
Function
This means that the slave
has received a stop (this bit is
7 I2CSGOTSTOP read only). Reset only when
the master begins a new
transmission.
Flag that indicates that no
6
I2CNOACK
acknowledge has been
received. Is reset at the start
of the next transaction
5
I2CSDA
Value of SDA line.
4
I2CDATACK Data acknowledge phase.
3
I2CIDLE
Indicates that I2C is idle
2
I2CRXOV
I2C Receiver overrun
1
I2CRXAV
I2C Receiver available
0
I2CTXEMP
I2C Transmitter empty
The I2CCHIPID register holds the VMX51C1020
I²C interface ID as well as the status bit that
indicates if the last byte monitored on the I²C
interface was destined for the VMX51C1020 or
not.
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