STC705 Datasheet, PDF (5/7 Pages) List of Unclassifed Manufacturers – UP Supervisor Circuits

Data Sheet
STC705-706/706P-707-708-708T/S/R-813L
µP Supervisor Circuits
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Functional Description
Watchdog Timer
The STCxxx family can assert reset output during power-up,
power-down and brownout conditions for uP system, detect
power failure or low-battery conditions with a 1.25V threshold
detector and have watchdog functions. Refer to Table 2 for
their individual features. The typical application see Figure 4.
Reset Output
The watchdog circuit monitors the µP’s activity. If the µP does
not toggle the watchdog input (WDI) within 1.6sec and WDI is
not in high impedance, WDO goes low. As long as RESET is
asserted or the WDI input is in high impedance, the watchdog
timer will stay cleared and will not count. As soon as reset is
released and WDI is driven high or low, the timer will start
counting. Pulses as short as 50ns can be detected.
The supervisory circuits can assert reset for a microprocessor
during power-up, power-down and brownout to prevent code
execution errors.
On power-up, once V_CC reaches about 1.2V, RESET is a
guaranteed logic low of 0.4V or less. As V_CC rises, RESET stays
low. When V rises above the reset threshold, an internal timer
CC
releases RESET after about 200ms. RESET pulses low whenever
V_CC drops below the reset threshold (brownout condition). If
brownout occurs in the middle of a previously initiated reset
pulse, the pulse continues for at least another 140ms.
Typically, WDO will be connected to the non-maskable
interrupt input (NMI) of a µP. When V_CC drops below the reset
threshold, WDO will go low whether or not the watchdog timer
has timed out yet. Normally this would trigger an NMI
interrupt, but RESET goes low simultaneously, and thus
overrides the NMI interrupt. If WDI is left unconnected, WDO
can be used as a low-line output. Since floating WDI disables
the internal timer, WDO goes low only when V_CC falls below
the reset threshold, thus functioning as a low-line output.
Manual Reset
On power-down, once V_CC falls below the reset threshold,
RESET stays low and is guaranteed to be 0.4V or less until Vcc
drops below 1V.
The STC813x and STC706P active-high RESET output is
simply the complement of the RESET output, and is guaranteed
to be valid with V_CC down to 1.2V. Some µPs, such as Intel’s
80C51, require an active-high reset pulse.
The manual-reset input (MR) allows reset to be triggered by a
push-button switch. The switch is effectively debounced by
the 140ms minimum reset pulse width. MR is TTL/CMOS
logic compatible, so it can be driven by any logic reset output.
Power-Fail Comparator
The power-fail comparator will send out a Low signal once
detects a voltage lowered than 1.25V. It can be used for various
purposes because its output and non-inverting input are not
internally connected. The inverting input is internally
connected to a 1.25V reference.
Figure 4. Typical Application Circuit
IN DC Linear
Regulator
OUT
Vcc
RESET
µP Supervisory
PFI Circuit WDI
WDO
MR
PFO
µP
Vcc
RESET
I/O Line
NMI
Interrupt
STC
5
Ver1.0