NT256D64S88AAG Datasheet, PDF (5/15 Pages) List of Unclassifed Manufacturers – 184pin One Bank Unbuffered DDR SDRAM MODULE

NT256D64S88AAG
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM
Serial Presence Detect -- Part 1 of 2
32Mx64 SDRAM DIMM based on 32Mx8, 4Banks, 8K Refresh, 2.5V DDR SDRAMs with SPD
Byte
Description
SPD Entry Value
Serial PD Data Entry (Hexadecimal) Note
DDR266A DDR266B DDR200 DDR266A DDR266B DDR200
-7K
-75B
-8B
-7K
-75B
-8B
Number of Serial PD Bytes Written during
0
128
80
Production
1 Total Number of Bytes in Serial PD device
256
08
2 Fundamental Memory Type
SDRAM DDR
07
3 Number of Row Addresses on Assembly
13
0D
4 Number of Column Addresses on Assembly
10
0A
5 Number of DIMM Bank
1
01
6 Data Width of Assembly
X64
40
7 Data Width of Assembly (cont’)
X64
00
8 Voltage Interface Level of this Assembly
SSTL 2.5V
04
9 DDR SDRAM Device Cycle Time at CL=2.5
7ns
7.5ns
8ns
70
75
80
DDR SDRAM Device Access Time from
10
0.75ns 0.75ns
0.8ns
75
75
80
Clock at CL=2.5
11 DIMM Configuration Type
Non-Parity
00
12 Refresh Rate/Type
SR/1x(7.8µs)
82
13 Primary DDR SDRAM Width
X8
08
14 Error Checking DDR SDRAM Device Width
N/A
00
DDR SDRAM Device Attr: Min CLk Delay,
15
1 Clock
01
Random Col Access
DDR SDRAM Device Attributes:
16
2,4,8
0E
Burst Length Supported
DDR SDRAM Device Attributes: Number of
17
4
04
Device Banks
DDR SDRAM Device Attributes: CAS
18
Latencies Supported
2/2.5
2/2.5
2/2.5
0C
0C
0C
19 DDR SDRAM Device Attributes: CS Latency
0
01
20 DDR SDRAM Device Attributes: WE Latency
1
02
21 DDR SDRAM Device Attributes:
Differential Clock
20
22 DDR SDRAM Device Attributes: General
+/-0.2V Voltage Tolerance
00
23 Minimum Clock Cycle at CL=2
7.5ns
10ns
10ns
75
A0
A0
Maximum Data Access Time from Clock at
24
0.75ns 0.75ns
0.8ns
75
75
80
CL=2
25 Minimum Clock Cycle Time at CL=1
N/A
00
Maximum Data Access Time from Clock at
26
N/A
00
CL=1
27 Minimum Row Precharge Time (tRP)
20ns
20ns
20ns
50
50
50
Minimum Row Active to Row Active delay
28
15ns
15ns
15ns
3C
3C
3C
(tRRD)
29 Minimum RAS to CAS delay (tRCD)
20ns
20ns
20ns
50
50
50
30 Minimum RAS Pulse Width (tRAS)
45ns
45ns
50ns
2D
2D
32
31 Module Bank Density
256MB
40
Address and Command Setup Time Before
32
0.9ns
0.9ns
1.1ns
90
90
B0
Clock
Address and Command Hold Time After
33
0.9ns
0.9ns
1.1ns
90
90
B0
Clock
34 Data Input Setup Time Before Clock
0.5ns
0.5ns
0.6ns
50
50
60
35 Data Input Hold Time After Clock
0.5ns
0.5ns
0.6ns
50
50
60
36-61 Reserved
Undefined
00
62 SPD Revision
Initial
Initial
Initial
00
00
00
63 Checksum Data
8F
BF
45
REV 1.1
08/2002
5
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