MRD520A Datasheet, PDF (5/9 Pages) List of Unclassifed Manufacturers – 1.2um CMOS integrated circuit for purpose of amplification

Uniform Industrial Corp.
MRD520A
Dual Channel F2F Decoder IC
5. FUNCTION DESCRIPTION
Data signal inputs read from a magnetic card via a magnetic head are fed into the SEN1P
and SEN1N (SEN2P and SEN2N) pins, amplified and wave shaped by internal analog
circuitry, then converted to logic level F2F data format. Once the F2F signals are detected,
the decoding logic ignores the leading 4 or 8 bits (set by IBS pin), via the ignored bits the
reference bit length is determined. The succeeding inputs are identified as bit 0 or 1 by
the average bit length of preceding two bits, if the data toggles before 70% of the
reference bit length then the data is identified as a “1” bit and the next data toggle regarded
as the beginning of next data bit. If the data toggles after 70% of the reference bit length
then the data is identified as a “0” bit and the current data toggle is as the beginning of next
data.
After the ignored bits, then pin CLS will be pulled low, the succeeding data bit will be shifted
out after the beginning of next data bit.
The pin OCK1 (OCK2) will be pulled low after the next data is detected and a 12uS delay
inserted, it will be kept low for 14 to 60uS depending on the external resistor connected to
pin ADJ1 (ADJ2). If the next bit comes before OCK1 (OCK2) goes high, then OCK1
(OCK2) will be forced to pull high and then begins next cycle, it means that the data signals
will be ready before OCK1 (OCK2) goes low and stay valid till 12uS before next down edge
of OCK1 (OCK2).
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October, 1997