CH7009A Datasheet, PDF (5/46 Pages) List of Unclassifed Manufacturers – Chrontel CH7009 DVI / TV Output Device

CHRONTEL
Table 1: Pin Description
64-Pin _{# Pins Type}
LQFP
46
1
Out
47
1
Out
48
1
Out
50 – 55, 12
58 – 63
57, 56
2
In / Out
In
1, 12, 49 3
6, 11, 64 3
45
1
23, 29
2
20, 26, 32 3
18, 44
2
16, 17, 41 3
33
1
34, 40
2
Power
Power
Power
Power
Power
Power
Power
Power
Power
CH7009A
Symbol Description
P-OUT /
TLDET*
Pixel Clock Output / DVI Link Detect Output
When the CH7009 is operating as a VGA to TV encoder in
master clock mode, this pin provides a pixel clock signal to the
VGA controller which is used as a reference frequency. The
output is selectable between 1X or 2X of the pixel clock
frequency. The output driver is driven from the DVDDV
supply. This output has a programmable tri-state. The
capacitive loading on this pin should be kept to a minimum.
BCO
When the CH7009 is operating as a DVI transmitter, this pin
provides an open drain output which pulls low when a
termination change has been detected on the HPDET input.
The output is released through IIC control.
Buffered Clock Output
C/H SYNC
This output pin provides a buffered clock output, driven by the
DVDD supply. The output clock can be selected using the BCO
register.
Composite / Horizontal Sync Output
This pin can be selected to output a TV composite sync, TV
horizontal sync, or a buffered version of the VGA horizontal
sync. The output is driven from the DVDD supply.
D[11] - D[0] Data[11] through Data[0] Inputs
XCLK,
These pins accept the 12 data inputs from a digital video
port of a graphics controller. The levels are 0 to DVDDV,
and the VREF signal is used as the threshold level.
External Clock Inputs
XCLK*
These inputs form a differential clock signal input to the
CH7009 for use with the H, V, DE and D[11:0] data. If
differential clocks are not available, the XCLK* input
should be connected to VREF.
DVDD
DGND
DVDDV
TVDD
TGND
AVDD
AGND
VDD
GND
The output clocks from this pad cell are able to have their
polarities reversed under the control of the MCP bit.
Digital Supply Voltage (3.3V)
Digital Ground
I/O Supply Voltage (3.3V to 1.1V)
DVI Transmitter Supply Voltage (3.3V)
DVI Transmitter Ground
PLL Supply Voltage (3.3V)
PLL Ground
DAC Supply Voltage (3.3V)
DAC Ground
201-0000-035 Rev 1.1, 5/8/2000
5