VT8601 Datasheet, PDF (42/144 Pages) List of Unclassifed Manufacturers – Single-Chip Slot-1 / Socket-370 PCI North Bridge With Integrated AGP 2D / 3D Graphics Accelerator and Advanced Memory Controller

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VT8601 Apollo ProMedia
Device 0 Bus 0 Host Bridge Registers
CPU Interface Control
Device 0 Offset 50 – Request Phase Control (00h) .........RW
7 CPU Hardwired IOQ (In Order Queue) Size
Default per strap on pin MA11 during reset. This
register bit can be written to 0 to restrict the chip to
one level of IOQ.
0 1-Level
1 4-Level ....... default if no external strap resistor
6 Read-Around-Write
0 Disable ...................................................default
1 Enable
5 Reserved ........................................ always reads 0
4 Defer Retry When HLOCK Active
0 Disable ...................................................default
1 Enable
Note: always set this bit to 1
3-2 Reserved ........................................ always reads 0
1 Fast Speculative Read
0 Disable ...................................................default
1 Enable
0 CPU / PCI Master Read DRAM Timing
0 Start DRAM read after snoop complete ...... def
1 Start DRAM read before snoop complete
Device 0 Offset 51 – Response Phase Control (00h)....... RW
7 CPU Read DRAM 0WS for Back-to-Back Read
Transactions
0 Disable................................................... default
1 Enable
Setting this bit enables maximum read performance
by allowing continuous 0-wait-state reads for
pipelined line reads. If this bit is not set, there will be
at least 1T idle time between read transactions.
6 CPU Write DRAM 0WS for Back-to-Back Write
Transactions
0 Disable................................................... default
1 Enable
Setting this bit enables maximum write performance
by allowing continuous 0-wait-state writes for
pipelined line writes ands sustained 3T single writes.
If this bit is not set, there will be at least 1T idle time
between write transactions.
5 DRAM Read Request Rate
0 3T .................................................... default
1 2T
4 Fast Response (HIT/HITM Sampled 1T Earlier)
0 Disable................................................... default
1 Enable
3 Non-Posted IOW
0 Disable................................................... default
1 Enable
2 CPU Read DRAM Prefetch Buffer Depth
0 1-level prefetch buffer ........................... default
1 4-level prefetch buffer
1 CPU-to-DRAM Post-Write Buffer Depth
0 1-level post-write buffer ........................ default
1 4-level post-write buffer
0 Concurrent PCI Master / Host Operation
0 Disable – the CPU bus will be occupied (BPRI
asserted) during the entire PCI operation..... def
1 Enable – the CPU bus is only requested before
ADS# assertion
Revision 1.3 September 8, 1999
-36-
Device 0 Bus 0 Host Bridge Registers