TH7301 Datasheet, PDF (4/14 Pages) List of Unclassifed Manufacturers – Dual-Channel Programmable Low-Pass Filter

TH7301 Dual-Channel Programmable Low-Pass Filter
Serial Interface
Programming
The serial interface is a 3-wire bus used to
program the filter cutoff frequency and voltage
gain. Pin SDATA is the serial data input for an 8-
bit shift register, SCLK is the shift register clock
(active positive edge), SDEN (active high) is the
serial interface enable. Note that logic levels are
referenced to a - 5 V supply and that there is no
global reset for the logic devices, so a reset word
should be input after power up.
The timing diagram for the interface is shown
below.
Operating
conditions
for the 3 wire
interface
Figure 3: Serial Interface Timing Diagram
Parameter
Symbol
Min
Typ
Max
Unit
Comments
Power supply voltage
VSS
-5.25
-5.0
-4.75
V
relative to VDD
High level input voltage
VIH
0.3 * VSS
VDD + 0.1V
note
Low level input voltage
VIL
VSS - 0.1V
0.7 * VSS
note
Serial data clock period
tCLK
50
ns
Serial data setup time
tSD
10
ns
Serial data hold time
tHD
10
ns
Serial data enable delay time
tDEN
20
ns
Serial data enable hold time
tHEN
20
ns
Notes: Logic threshold levels for inputs SCLK, SDATA and SDEN. Note that this is a negative supply IC.
The serial data is stored in one of 3 internal
registers - gain control, frequency select A and
frequency select B.
The first two bits of the serial data form an
address code for the registers. The gain control
bits AC(5...0) are decoded to select a voltage gain
between 0 dB and 20.5 dB in 0.5 dB steps. The
frequency select bits FC(2...0) select one of the
octave chords while FS(6...0) select the step
within each chord.
Additional bit OS0 (active high) controls the
oscillator (for test issues only). The table below
shows the address and data decoding of the serial
data input.
The serial interface does not contain a power on
reset, thus all three registers must be pro-
grammed after power on to prevent undefined
logical states and to achieve reliable filter opera-
tion. I. e. a first reset word may reset all registers
to 0.
Usage
Frequency Select A
Frequency Select B
Gain Control
Address Bits
Data Bits
D7
D6
D5
D4
D3
D2
D1
D0
0
0
FS2 FS1 FS0 FC2 FC1
FC0
0
1
OS0
0
FS6
FS5
FS4
FS3
1
1
AC5 AC4 AC3 AC2 AC1
AC0
4