STK16C68 Datasheet, PDF (4/9 Pages) List of Unclassifed Manufacturers – 8K x 8 AutoStorePlus™ nvSRAM QuantumTrap™ CMOS Nonvolatile Static RAM

STK16C68
SRAM WRITE CYCLES #1 & #2
(V_CC = 5.0V ± 10%)^b
SYMBOLS
NO.
#1
#2
Alt.
PARAMETER
STK16C68-20
MIN MAX
12 t_AVAV
t_AVAV
t_WC Write Cycle Time
20
13 t_WLWH
t_WLEH
t_WP Write Pulse Width
15
14 t_ELWH
t_ELEH
t_CW Chip Enable to End of Write
15
15 t_DVWH
t_DVEH
t_DW Data Set-up to End of Write
8
16 t_WHDX
t_EHDX
t_DH Data Hold after End of Write
0
17 t_AVWH
t_AVEH
t_AW Address Set-up to End of Write
15
18 t_AVWL
t_AVEL
t_AS Address Set-up to Start of Write
0
19 t_WHAX
t_EHAX
t_WR Address Hold after End of Write
0
20 t_WLQZ^{i, j}
t_WZ Write Enable to Output Disable
7
21 t_WHQX
t_OW Output Active after End of Write
5
Note j: If W is low when E goes low, the outputs remain in the high-impedance state.
Note k: E or W must be ≥ V_IH during address transitions.
SRAM WRITE CYCLE #1: W Controlled^k
ADDRESS
12
t_AVAV
14
t_ELWH
E
STK16C68-25 STK16C68-35 STK16C68-45
UNITS
MIN MAX MIN MAX MIN MAX
25
35
45
ns
20
25
30
ns
20
25
30
ns
10
12
15
ns
0
0
0
ns
20
25
30
ns
0
0
0
ns
0
0
0
ns
10
13
15
ns
5
5
5
ns
19
t_WHAX
W
DATA IN
DATA OUT
18
t_AVWL
17
t_AVWH
13
t_WLWH
20
t_WLQZ
PREVIOUS DATA
15
t_DVWH
DATA VALID
HIGH IMPEDANCE
16
t_WHDX
21
t_WHQX
SRAM WRITE CYCLE #2: E Controlled^k
ADDRESS
12
t_AVAV
18
t_AVEL
E
14
t_ELEH
19
t_EHAX
W
DATA IN
DATA OUT
17
t_AVEH
13
t_WLEH
15
t_DVEH
DATA VALID
HIGH IMPEDANCE
16
t_EHDX
July 1999
4-76