SED1336 Datasheet, PDF (4/12 Pages) List of Unclassifed Manufacturers – CMOS GRAPHIC LCD/TV CONTROLLER

SED1336
• ^{DC Electrical Characteristics}
VDD = 4.5 to 5.5V, VSS = 0V, Ta = –20 to 75°C
Parameter
Supply voltage
Register data retention voltage
Input leakage current
Output leakage current
Operating supply current
Quiescent supply current
Oscillator frequency
External clock frequency
Oscillator feedback resistance
TTL
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
LOW-level output voltage
CMOS
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
LOW-level output voltage
Open-drain
LOW-level output voltage
Schmitt-trigger
Rising-edge threshold voltage
Falling-edge threshold voltage
Symbol
Condition
Min
VDD
4.5
VHO
2.0
ILI
VI = VDD. See note 6.
—
ILO
VI = VSS. See note 6.
—
Iopr
See note 4.
—
IQ
Sleep mode,
VOSC1 = VCS = VRD = VDD
—
fOSC
Measured at crystal,
1.0
fCL
47.5% duty cycle.
1.0
Rf
See note 7.
0.5
Typ
5.0
—
0.05
0.10
11
0.05
—
—
1.0
Max
5.5
6.0
2.0
5.0
15
20.0
10.0
10.0
3.0
VIHT
VILT
V^OHT
VOLT
See note 1.
See note 1.
IOH = –5.0 mA.
See note 1.
IOL = 5.0 mA. See note 1.
0.8VDD
VSS
2.4
—
—
VDD
—
0.2VDD
—
—
— VSS + 0.4
VIHC
See note 2.
0.8VDD
—
VDD
VILC
See note 2.
VSS
—
0.2VDD
VOHC IOH = –2.0 mA. See note 2. VDD – 0.4 —
—
VOLC IOH = 1.6 mA. See note 2. —
— VSS + 0.4
VOLN IOL = 6.0 mA. See note 5. —
— VSS + 0.4
VT+
See note 3.
0.5VDD 0.7VDD 0.8VDD
VT–
See note 3.
0.2VDD 0.3VDD 0.5VDD
Unit
V
V
µA
µA
mA
µA
MHz
MHz
MΩ
V
V
V
V
V
V
V
V
V
V
V
Notes:
1. D0 to D7, A0, CS, RD, WR, VD0 to VD7, VA0 to VA15,
VRD, VWR and VCE are TTL-level inputs.
2. SEL1 and NT/PL are CMOS-level inputs. YD, XD0 to
XD3, XSCL, LP, WF, YDIS and CLO are CMOS-level
outputs.
3. RES is a Schmitt-trigger input. The pulsewidth on RES
must be at least 200 µs. Note that pulses of more than a
few seconds will cause DC voltages to be applied to the
LCD panel.
4. fOSC = 10 MHz, no load (no display memory), internal
character generator, 256 × 200 pixel display. The operat-
ing supply current can be reduced by approximately 1 mA
by setting both CLO and the display OFF.
5. SNC and VSD are n-channel, open-drain outputs. The
voltage on the outputs should not exceed VDD as internal
diodes connect the pins to VDD (SED1336F only).
6. VD0 to VD7 and D0 to D7 have internal feedback circuits
so that if the inputs become high-impedance, the input
state immediately prior to that is held. Because of the
feedback circuit, input current flow occurs when the
inputs are in an intermediate state.
7. Because the oscillator circuit input bias current is in the
order of µA, design the printed circuit board so as to
reduce leakage currents.
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