NM9715 Datasheet, PDF (4/17 Pages) List of Unclassifed Manufacturers – PCI Dual 1284 Printer Ports

Nm9715
PCI Dual 1284 Printer Ports
Pin Name 128
nRESET 121
Type
I
AD31-29 126-128
I/O
AD28-24 2-6
I/O
AD23-16 11-18
I/O
AD15-11 34-38
I/O
AD10-8 40-42
I/O
AD7-0 46-53
I/O
nFRAME 23
I
nIRDY
24
I
nTRDY
25
O
nSTOP
27
O
nLOCK
28
I
IDSEL
9
I
nDEVSEL 26
O
nPERR
29
O
Description
PCI system reset (active low). Resets all internal register, sequencers, and
signals to a consistent state. During reset condition, AD31-0 and nSER are
three-stated.
Multiplexed PCI address/data bus. A bus transaction consists of an address
phase followed by one or more data phases. During the address phase AD31-
0 contain a physical address. Write data is stable and valid when nIRDY and
nTRDY are asserted (active).
See AD31-29 description.
See AD31-29 description.
See AD31-29 description.
See AD31-29 description.
See AD31-29 description.
Frame is driven by the current master to indicate the beginning and duration
of an access. nFRAME is asserted to indicate a bus transaction is beginning.
While nFRAME is active, data transfer continues.
Initiator Ready. During a write, nIRDY asserted indicates that the initiator is
driving valid data onto the data bus. During a read, nIRDY asserted indicates
that the initiator is ready to accept data from the Nm9715.
Target Ready (three-state). It is asserted when Nm9715 is ready to complete
the current data phase.
Nm9715 asserts nSTOP to indicate that it wishes the initiator to stop the
transaction in process on the current data phase.
Lock indicates an atomic operation that may require multiple transactions to
complete.
Initialization Device Select. It is used as a chip select during configuration
read and write transactions.
Device Select (three-state). Nm9715 asserts nDEVSEL when the Nm9715
has decoded its address.
Parity Error (three-state). Is used to report parity errors during all PCI trans-
actions except a special cycle. The minimum duration of nPERR is one clock
cycle.
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Rev. 1.2