AC-PLM-1 Datasheet, PDF (4/7 Pages) List of Unclassifed Manufacturers – AC-PLM-1 Powerline Modem

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Pin Name Type
CK
HCK
INT²
HSK²
VDDCORE
VSSOUT
OSCI
VDDOUT
VSSCORE
PORT0^1,2
PORT1^1,2
PORT2^1,2
PORT3^1,2
PORT4^1,2
PORT5^1,2
Output
Output
Output
Tri-state
VCC
GND
Input
VCC
GND
Inout
Inout
Inout
Inout
Inout
Input
PORT6^1,2
PORT7^1,2
POEN3²
POEN4²
Input
Input
Output
Output
PORTYPE^1,2
CSPOL^1,2
RCVNG
XING
IN²
XOUT²
Input
Input
Output
Output
Input
Output
XOUTE²
RESET
CNFGD
SCAN_EN³
RBURSTP
RSOPP
REOF
REOP
RBIT
RBITSTR
LBUSY
XBITOUT
XBITSTR
XCMD
TESTMODE
Output
Output
Output
Input
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Pin
No.
1
2
3
4
5,27
6,30
7
8,28
9,31
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
29
32
33
34
35
36
37
38
39
40
41
42
43
44
Drive Functions
(mA)
1 Frequency carrier = OSCI/XDVI.
1 OSCI clock output.
2 Interrupt.
2 Handshake signal.
-
3.3V input.
-
Ground signal.
-
Input clock signal.
-
3.3V input.
-
Ground signal.
2 Data IO 0 / Data available on the communication port.
2 Data IO 1 / Line busy indication.
2 Data IO 2 / Communication port busy indication.
2 Data IO 3 / Serial data in (SDI).
2 Data IO 4 / Serial data out (SDO).
-
Clock polarity in serial mode / read-write enable in parallel
mode. Read = 1’b1.
-
Strobe or clock signal.
-
Chip Select.
2 Port output enable for PORT3. Output when POEN3 = 1.
2 Port output enable for PORT0, 1, 2 and 4. Output when
POEN4 = 1.
-
Communication port type. 1 = Parallel, 0 = serial.
-
Chip Select polarity. 1 = CS active high.
8 Receiving a valid packet. Can drive a LED. Active low.
8 Transmitting a valid packet. Can drive a LED. Active low.
-
Receiver input.
1 Transmitter output. Need to be filtered to eliminate second
frequency generated by the chip.
1 Amplifier enable signal.
-
Hardware reset. Active low. Internal pull-up.
-
Configuration status. Active high. Can drive a LED.
-
Use to internal test. Internal pull-down. Must be tied to GND.
1 DEBUG pin. Receiver burst pulse. No connect.
1 DEBUG pin. Receiver side. Start of packet pulse. No connect.
1 DEBUG pin. Receiver side. End of field. No connect.
1 DEBUG pin. Receiver side. End of packet. No connect.
1 DEBUG pin. Receiver side. A bit of a packet.
1 DEBUG pin. Receiver side. Strobe to validate a RBIT.
1 DEBUG pin. Line busy indicator.
1 DEBUG pin. TX side. Output bit before modulation.
1 DEBUG pin. TX side. Output bit strobe.
1 DEBUG pin. TX side. Command indicator.
1 Use by BIST test. Internal pull-down. Must be tied to GND.
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