MC55000 Datasheet, PDF(32/43 Page) List of Unclassifed Manufacturers – Electrical Specification for Pulse and Direction Motion Control

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MC55000 Datasheet, PDF (32/43 Pages) List of Unclassifed Manufacturers – Electrical Specification for Pulse and Direction Motion Control

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5.1.1

MC55110 CP chip pin description

Pin Name and number Direction

~Reset

133 input

~WriteEnable 89

output

~ReadEnable 93

output

~Strobe

96 output

R/~W

92 output

W/~R

Ready

19 output

120 input

~PeriphSlct 82

output

~RAMSlct

output

SrlXmt

25 output

SrlRcv

26 input

CANXmt

SrlEnable

72 output

CANRcv

SPIClock

70 output

35 output

SPIXmt

30 output

IOInterrupt

input

MasterClkIn 123 input

ClockOut

73 output

Description

This is the master reset signal. When brought low, this pin resets the chipset to its

initial conditions.

This signal is the write-enable strobe. When low, this signal indicates that data is

being written to the bus.

This signal is the read-enable strobe. When low, this signal indicates that data is

being read from the bus.

This signal is low when the data and address are valid during CP

communications. If the parallel interface is used, this pin should be connected

to the PLD/FPGA IO chip signal CPStrobe.

This signal is high when the CP chip is performing a read, and low when it is

performing a write. If the parallel interface is used, this pin should be connected

to the PLD/FPGA IO chip signal CPR/~W.

This signal is the inverse of R/~W; it is high when R/~W is low, and vice versa. For

some decode circuits and devices this is more convenient than R/~W.

Ready can be pulled low to add wait states for external accesses. Ready indicates

that an external device is prepared for a bus transaction to be completed. If the

device is not ready, it pulls the Ready pin low. The motion processor then waits

one cycle and checks Ready again.

This signal can be left unconnected if it is not used.

This signal is low when peripheral devices on the data bus are being addressed. If

the parallel interface is used, this pin should be connected to the PLD/FPGA

IO chip signal CPPeriphSlct.

This signal is low when external memory is being accessed.

This pin outputs serial data from the asynchronous serial port.

This pin inputs serial data to the asynchronous serial port.

When the CAN host interface is used, this pin transmits serial data to the CAN

transceiver.

When the multi-drop serial interface is used, this pin sets the serial port enable

line and the CANXmt function is not available. SrlEnable is high during

transmission for the multi-drop protocol and low at all other times.

This pin receives serial data from the CAN transceiver.

This pin is the clock signal used for strobing synchronous serial data to the serial

DAC(s). This signal is only active when SPI data is being transmitted.

This pin transmits synchronous serial data to the serial DAC(s).

This interrupt signal is used for IO to CP communication. If the parallel

interface is used, this pin should be connected to the PLD/FPGA IO chip signal

CPInterrupt.

This signal can be left unconnected if it is not used.

This is the clock signal for the Motion Processor. It is driven at a nominal

20MHz.

This signal is the reference output clock. Its frequency is twice the frequency of

the input clock (which is normally 20MHz) resulting in a nominal output

frequency of 40MHz.

MC55000 Electrical Specification â Preliminary 11/14/2003

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