M32L1632512A Datasheet, PDF (32/54 Pages) List of Unclassifed Manufacturers – 256K x 32 Bit x 2 Banks Synchronous Graphic RAM

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M32L1632512A
FUNCTION TRUTH TABLE (TABLE 1, Continued)
*Note : 1. All entries assume the CKE was active (High) during the preceding clock cycle and the current clock cycle.
2. Illegal to bank in specified state ; Function may be legal in the bank indicated by BA, depending on the state of that
bank.
3. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
4. NOP to bank precharging or in idle state. May precharge bank indicated by BA (and PA).
5. Illegal if any bank is not idle.
6. Legal only if all banks are in idle or row active state.
FUNCTION TRUTH TABLE for CKE (TABLE2)
Current
State
CKE
( n-1 )
CKE
n
CS
RAS CAS WE DSF
ADDR
ACTION
Note
H
X XX X XX
X INVALID
L
H HX X XX
X
Æ Exit Self Refresh ÂÃÊ after tRC
7
Self
L
H L H H HX
X
Æ Exit Self Refresh ÂÃÊ after tRC
7
Refresh
L
H L H H L X X ILLEGAL
L
H L H L X X X ILLEGAL
L
H L L X X X X ILLEGAL
L
L X X X X X X NOP (Maintain Self Refresh)
Both
Bank
H
L
L
X XX X XX
H HX X XX
H L H H HX
X
X
X
INVALID
Æ Exit Power Down ABI
Æ Exit Power Down ABI
8
8
Precharge L
H L H H L X X ILLEGAL
Power
L
H L H L X X X ILLEGAL
Down
L
H L L X X X X ILLEGAL
L
L X X X X X X NOP (Maintain Low Power Mode)
H
H XX X XX
X Refer to Table 1
H
L H X X X X X Enter Power Down
9
H
L L H H H X X Enter Power Down
9
All
H
L L H H L X X ILLEGAL
Banks
H
L L H L X X X ILLEGAL
Idle
H
L L L H X X X ILLEGAL
H
L L L L H X X Enter Self Refresh
9
H
L L L L L X X ILLEGAL
L
L X X X X X X NOP
Any State H
H X X X X X X Refer to Operations in Table 1
other than H
L X X X X X X Begin Clock Suspend next cycle
10
Listed
L
H X X X X X X Exit Clock Suspend next cycle
10
Above
L
L X X X X X X Maintain Clock Suspend
ABBREVIATIONS : ABI = All Banks Idle
*Note : 7.After CKE’s low to high transition to exit self refresh mode. And a time of tRC(min) has to be elapse after CKE’s low to
high transition to issue a new command.
8.CKE low to high transition is asynchronous as if restart internal clock.
A minimum setup time “ tSS + one clock “ must be satisfy before any command other than exit.
9.Power down and self refresh can be entered only from the all banks idle state.
10.Must be a legal command.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2001
Revision : 1.6
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