GS832218 Datasheet, PDF (29/41 Pages) List of Unclassifed Manufacturers – 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs

Preliminary
GS832218(B/E)/GS832236(B/E)/GS832272(C)
JTAG TAP Block Diagram
····· ···
Boundary Scan Register
·
·
·
0
Bypass Register
210
Instruction Register
TDI
TDO
ID Code Register
· 31 30 29 · · · 2 1 0
Control Signals
TMS
TCK
Test Access Port (TAP) Controller
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
ID Register Contents TBD for this part.
Rev: 1.06 9/2004
29/41
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, GSI Technology