SD1010D Datasheet, PDF (28/40 Pages) List of Unclassifed Manufacturers – Digital Interface VGA TFT LCD Display Controller

Lookup Enable
Vertical Table
1
Lookup Enable
HSYNC Threshold 1
Enable
OSD Intensity
1
Load ALL EEPROM 1
Load Mode
1
Dependent EEPROM
CPU control enable 1
Status 0
8
Status 1
4
Control_A
8
Control_B
8
1: enable horizontal Table Lookup
0: disable horizontal Table Lookup
RW 28H[0] Enable vertical Table Lookup (default 0):
1: enable vertical Table Lookup
0: disable vertical Table Lookup
RW 29H[4] Enable detection of short lines (IBM panel only,
default 0):
1: Enable such detection
0: disable such detection
RW 29H[3] OSD intensity selection:
0: half intensity
1: full intensity
RW 29H[2] Should be kept low most of the time. A high pulse will
force SD1010 to reload all EEPROM entries
RW 29H[1] Should be kept low most of the time. A high pulse will
force SD1010 to reload mode dependent EEPROM
entries
RW 29H[0] External CPU control enable:
0: disable external CPU control. SD1010 can write
control registers, but CPU only read control registers.
1: enable external CPU control. CPU can read/write
control registers. SD1010 cannot write control
registers
R
2AH Read only internal status registers:
1: indicate error status
0: indicate normal status
Bit 0: EEPROM gamma correction table loading
Bit 1: EERPOM gamma correction table loading
Bit 2: EEPROM mode dependent entries loading
Bit 3: EEPROM calibration entries loading
Bit 4: input has too few lines
Bit 5: no input video
Bit 6: input data clock is too fast
Bit 7: refresh rate exceed LCD panel specification
R 2BH[3:0] Internal auto calibration state
0: Idle State
1-4: Loading EEPROM data
5-9: Frequency Calibration State (Auto Frequency
Calibration will be done after state 9)
10: Phase Calibration State (Auto Phase Calibration
will be done after state 10)
11: Adjust Horizontal Back Porch state
12: Phase Tracking state
RW 2CH[7:0] Control Register A:
0 – disable
1 – enable
default is 00H
Bit 0: Horizontal Interpolation Offset Enable
Bit 1: Vertical Interpolation Offset Enable
Bit 2: Horizontal Interpolation Fraction Reset Enable
Bit 3: Vertical Interpolation Fraction Reset Enable
Bit 4: Horizontal Interpolation Integer Increment
Enable
Bit 5: Vertical Interpolation Integer Increment Enable
Bit 6: Single Pixel Output Mode Enable
Bit 7: Disable “DE_OUT”, for blanking screen purpose
RW 2DH[7:0] Control Register B
525 Race Street, Suite 250, San Jose, CA 95126, USA.
Main: [phone] Fax: [phone]