DOC7707 Datasheet, PDF (266/307 Pages) List of Unclassifed Manufacturers – Microcontroller with 8/16K Bytes of ISP Flash and USB Controller

Note:
1. In SPI Programming mode the minimum SCK high/low period is:
- 2 t_CLCL for f_CK < 12 MHz
- 3 t_CLCL for f_CK > 12 MHz
Figure 26-3. SPI Interface Timing Requirements (Master Mode)
SS
6
1
SCK
(CPOL = 0)
2
2
SCK
(CPOL = 1)
45
3
MISO
(Data Input)
MSB
...
7
LSB
8
MOSI
(Data Output)
MSB
...
LSB
Table 26-3. SPI Interface Timing Requirements (Slave Mode)
SS
9
SCK
(CPOL = 0)
SCK
(CPOL = 1)
13
14
MOSI
(Data Input)
MSB
...
15
MISO
(Data Output)
MSB
...
10
16
11
11
12
LSB
17
LSB
X
26.7 Hardware Boot EntranceTiming Characteristics
Figure 26-4. Hardware Boot Timing Requirements
RESET
ALE/HWB
t_SHRH
t_HHRH
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