CH7013A Datasheet, PDF(25/46 Page) List of Unclassifed Manufacturers

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CH7013A Datasheet, PDF (25/46 Pages) List of Unclassifed Manufacturers – Digital PC to TV Encoder

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CHRONTEL

CH7013A

Registers and Programming

The CH7013A is a fully programmable device, providing for full functional control through a set of registers

accessed from the serial port. The CH7013A contains a total of 37 registers, which are listed in Table15 and

described in detail under Register Descriptions. Detailed descriptions of operating modes and their effects are con-

tained in the previous section, Functional Description. An addition (+) sign in the Bits column below signifies that

the parameter contains more than 8 bits, and the remaining bits are located in another register.

Table 15. Register Map

Display Mode

Flicker Filter

Video Bandwidth

Input Data Format

Clock Mode

Start Active Video

Position Overflow

Black Level

Horizontal Position

Vertical Position

Symbol

DMR

FFR

VBW

IDF

SAV

BLR

HPR

VPR

Address

00H

01H

03H

04H

06H

07H

08H

09H

0AH

0BH

Sync Polarity

Power Management

Connection Detect

Contrast Enhancement

PLL M and N extra bits

PLL-M Value

PLL-N Value

Buffered Clock

Subcarrier Frequency

Adjust

PLL and Memory Control

CIV Control

Calculated Fsc Increment

Value

Version ID

Test

Address

SPR

PMR

CDR

MNE

PLLM

PLLN

BCO

FSCI

PLLC

CIVC

CIV

VID

0DH

0EH

10H

11H

13H

14H

15H

17H

18H -1FH

20H

21H

22H - 24H

25H

26H - 29H

3FH

Bits

4 or 8

each

8 each

Functional Summary

Display mode selection

Flicker filter mode selection

Luma and chroma filter bandwidth selection

Data format and bit-width selections

Sets the clock mode to be used

Active video delay setting

MSB bits of position values

Black level adjustment input latch clock edge select

Enables horizontal movement of displayed image on

Enables vertical movement of displayed image on

Determines the horizontal and vertical sync polarity

Enables power saving modes

Detection of TV presence

Contrast enhancement setting

Contains the MSB bits for the M and N PLL values

Sets the PLL M value - bits (7:0)

Sets the PLL N value - bits (7:0)

Determines the clock output at pin 41

Determines the subcarrier frequency

Controls for the PLL and memory sections

Control of CIV value

Readable register containing the calculated

subcarrier increment value

Device version number

Reserved for test (details not included herein)

Current register being addressed

201-0000-041 Rev. 1.0, 6/14/2000

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