STK18TA8 Datasheet, PDF (24/28 Pages) List of Unclassifed Manufacturers – nvTime Event Data Recorder Serial Peripheral Interface nvSRAM QuantumTrap CMOS Nonvolatile Static RAM

STK18TA8
0x1FFF8
OSCEN
Calibration
Sign
Calibration
Calibration / Control
D7
D6
D5
D4
D3
D2
D1
D0
OSCEN
0
Calibration
Sign
Calibration
Oscillator Enable. When set to 1, the oscillator is halted. When set to 0, the oscillator runs.
Disabling the oscillator saves battery/capacitor power during storage. On a no-battery power-up,
this bit is set to 0.
Determines if the calibration adjustment is applied as an addition to or as a subtraction from the
time-base.
These five bits control the calibration of the clock.
0x1FFF7
WDS
WDW
WDT
Watchdog Timer
D7
D6
D5
D4
D3
D2
D1
D0
WDS WDW
WDT
Watchdog Strobe. Setting this bit to 1 reloads and restarts the watchdog timer. Setting the bit to 0
has no affect. The bit is cleared automatically once the watchdog timer is reset. The WDS bit is
write only. Reading it always will return a 0.
Watchdog Write Enable. Setting this bit to 1 masks the watchdog time-out value (WDT5-WDT0) so
it cannot be written. This allows the user to strobe the watchdog without disturbing the time-out
value. Setting this bit to 0 allows bits 5-0 to be written on the next write to the Watchdog register.
The new value will be loaded on the next internal watchdog clock after the write cycle is complete.
This function is explained in more detail in the watchdog timer section.
Watchdog time-out selection. The watchdog timer interval is selected by the 6-bit value in this
register. It represents a multiplier of the 32 Hz count (31.25 ms). The minimum range or time-out
value is 31.25 ms (a setting of 1) and the maximum time-out is 2 seconds (setting of 3Fh). Setting
the watchdog timer register to 0 disables the timer. These bits can be written only if the WDW bit
was cleared to 0 on a previous cycle.
0x1FFF6
WIE
AIE
PFIE
ABE
H/L
P/L
Interrupt Status / Control
D7
D6
D5
D4
D3
D2
D1
D0
WIE
AIE
PFIE
ABE
H/L
P/L
0
0
Watchdog Interrupt Enable. When set to 1 and a watchdog time-out occurs, the watchdog timer
drives the INT pin as well as the WDF flag. When set to 0, the watchdog time-out affects only the
WDF flag.
Alarm Interrupt Enable. When set to 1, the alarm match drives the INT pin as well as the AF flag.
When set to 0, the alarm match only affects the AF flag.
Power-Fail Enable. When set to 1, the alarm match drives the INT pin as well as the AF flag. When
set to 0, the power-fail monitor affects only the PF flag.
Alarm Battery-backup Enable. When set to 1, the alarm interrupt (as controlled by AIE) will function
even in battery backup mode. When set to 0, the alarm will occur only when Vcc>Vswitch.
High/Low. When set to a 1, the INT pin is driven active high. When set to 0, the INT pin is open
drain, active low.
Pulse/Level. When set to a 1, the INT pin is driven active (determined by H/L ) by an interrupt
source for approximately 200 ms. When set to a 0, the INT pin is driven to an active level (as set
by H/L ) until the Flags/Control register is read.
April 2005
24
Document Control #ML0028 rev 0.8