VMODTFT_RM Datasheet, PDF (2/5 Pages) List of Unclassifed Manufacturers – VmodTFT™ Reference Manuall

VmodTFT Reference Manual
Figure 1 Power-Up Sequence
Description
Min Max Unit
t1 TFT-EN high to first
0.05 100 ms
pixel bus signal
t2 Valid pixel data to DISP 0 200 ms
high
t3 DISP high to backlight 160
ms
on;
backlight off to DISP
low
t4 TFT-EN low pulse
100
ms
Table 1 Power-Up/Reset Timing
Parameter
fCLK
tVA
tVB
tHA
tHB
Description
Pixel clock
Vertical active
period
Vertical
blanking
period
Horizontal
active period
Horizontal
blanking
period
Value Unit
9
MHz
272 lines
16 lines
480 CLK
periods
45 CLK
periods
Table 2 Typical LCD Video Timing Parameters
Video Timing
To display an image, the LCD needs to be
continuously driven with properly-timed data.
This data consists of the lines and blanking
periods that form video frames. Each frame
consists of 272 active lines and several vertical
blanking lines. Each line consists of 480 active
pixel periods and several horizontal blanking
periods.
Figure 2 Video Timing
Video data is sent on a parallel interface
synchronous to CLK. The table below lists the
timing parameters of this interface. “Data”
refers to the combined pixel data from the R,
G, and B pins.
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