818L8B Datasheet, PDF (2/13 Pages) List of Unclassifed Manufacturers – 2 X 4 8-Pole Filters

818 Series
8-Bit Programmable Filters
Digital Tuning &
Control Characteristics
Digital Tuning Characteristics
Pin-Out Key
The digital tuning interface circuits are two 4042 quad CMOS
latches which accept the following CMOS-compatible inputs:
eight tuning bits (D₀ - D₇), a latch strobe bit (C), and a transition
polarity bit (P).
Filter tuning follows the tuning equation given below:
fc = ( fmax/256 ) [ 1 + D₇ x 2⁷ + D₆ x 2⁶ + D₅ x 2⁵ + D₄ x 2⁴ + D₃ x
2³ + D₂ x 2² + D₁ x 2¹ + D₀ x 2⁰ ]
where D₁ - D₇ = "0" or "1", and
fmax = Maximum tuning frequency;
fc = corner frequency;
Minimum tunable frequency = fmax/256 (D₀ thru D₇ = 0);
Minimum frequency step (Resolution) = fmax/256
Data Control Specifications
Data Control Lines
Functions
Latch Strobe (C)
Transition Polarity (P)
IN Analog Input Signal
D₇ Tuning Bit 7 (MSB)
OUT Analog Output Signal
D₆ Tuning Bit 6
GND Power and Signal Return
D₅ Tuning Bit 5
"P" Transition Polarity Bit
D₄ Tuning Bit 4
"C" Tuning Strobe Bit
D₃ Tuning Bit 3
+Vs Supply Voltage, Positive
D₂ Tuning Bit 2
-Vs Supply Voltage, Negative
D₁ Tuning Bit 1
Os Optional Offset Adjustment
D₀ Tuning Bit 0 (LSB)
NC No Connect (Highpass Models)
OUT +Vs -Vs
D₇
D₆
D₅
D₄
GND
D₃
D₂
D1
D₀
Data Control Modes
Mode 1
P = 0; C = 0 frequency follows input codes
P = 0; C = 0⇑ frequency latched on rising edge
Mode 2
P = 1; C = 1 frequency follows input codes
P = 1; C = 1⇓ frequency latched on falling edge
Input Data Levels (CMOS Logic)
Input Voltage (Vs = 15 Vdc)
Low Level In
0 Vdc min.
High Level In
11 Vdc min.
4 Vdc max.
15 Vdc max.
Input Current
High Level In
Low Level In
- 10 ^-5 µA typ. -1 mA max.
+10 ^-5 µA typ. +1 µA max.
Input Capacitance
Latch Response
Data Set Up Time¹
Data Hold Time²
Strobe Pulse Width
5 pF typ
25 nS
50 nS
80 nS min.
7.5 pF max.
Input Data Format
Positive Logic
Bit Weighting
D₀
D₇
Frequency Range
Frequency Select Bits
Logic "1" = +Vs
Logic "0" = Gnd
(Binary-Coded)
LSB (least significant bit)
MSB (most significant bit)
256 : 1, Binary Weighted
IN Os/NC
MSB --- ---
2⁷ 2⁶ 2⁵
D₇ D₆ D₅
000
000
000
000
000
000
001
011
111
Bottom View
--- --- ---
2⁴ 2³ 2²
D₄ D₃ D₂
000
000
000
001
011
111
111
111
111
PC
---
LSB
Bit
Weight
2¹ 2⁰
fc
Corner
D₁ D₀ Frequency
0
0 fmax/256
0
1 fmax/128
1
1 fmax/64
1
1 fmax/32
1
1 fmax/16
1
1 fmax/8
1
1 fmax/4
1
1 fmax/2
1 1 fmax
Notes:
1.Frequency data must be present before occurrence of strobe edge.
2.Frequency data must be present after occurrence of strobe edge.
2
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