80-0208-B Datasheet, PDF (2/13 Pages) List of Unclassifed Manufacturers – Speech And Music Processor

SC-604
Data sheet
The data memory is internal static RAM. The RAM is configured in 640 17-bit words. All memories are designed
to consume minimum power at a given system clock and algorithm acquisition frequency.
A flexible clock generation system enables the software to control the clock over a wide frequency range. The
implementation uses a phase-locked loop (PLL) circuit that drives the processor clock at a selectable frequency
between the minimum and maximum achievable. Selectable frequencies for the processor clock are spaced
apart in 65.536-kHz steps. The PLL clock-reference is also selectable; either a resistor-trimmed oscillator or a
crystal-referenced oscillator may be used. Internal and external clock sources are controlled separately to
provide different levels of power management.
The periphery consists of two 8-bit-wide general-purpose I/O ports when operating in master mode, or four
general-purpose I/O pins in slave mode. In the master mode, the bidirectional I/O can be configured under
software control as either high-impedance inputs or as totem-pole output. They are controlled via addressable
I/O registers. These features make the input port especially useful as a key-scan interface. Slave mode consists
of four general-purpose I/O, four control pins, and eight bidirectional data pins.
A simple one-bit comparator is also included in the periphery. The comparator is enabled by a control register,
and its access is shared with two pins in one general-purpose I/O port. Rounding out the SC-604 periphery is a
built-in pulse-density-modulated DAC (digital-to-analog converter) with direct speaker-drive capability. The
following block diagram gives an overview of the SC-604functionality.
Functional block diagram
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P/N 80-0208-B
© 2002 Sensory Inc.