VRS700 Datasheet, PDF (19/45 Pages) List of Unclassifed Manufacturers – VERSA 700: 64kB FLASH, 4kB RAM 23MHz, 3V, 8-Bit MCU

VRS700
VERSA
Datasheet Rev 1.3
TABLE 21: SERIAL PORT CONTROL REGIS TER (SCON) – SFR 98H
7
6
5
4
3
2
1
0
SM0
SM1 SM2 REN
TB8 RB8 TI
RI
Bit Mnemonic Description
7
SM0
Bit to select mode of operation (see table
below)
6
SM1
5
SM2
Bit to select mode of operation (see table
below)
Multiprocessor communication is possible
in modes 2 and 3.
In modes 2 or 3, if SM2 is set to 1, RI will
not be activated if the received 9^th data bit
(RB8) is 0.
4
REN
3
TB8
2
RB8
In Mode 1, if SM2=1, RI will not be
activated if a valid stop bit was not
received.
Serial Reception Enable Bit.
This bit must be set by software and
cleared by software.
1: Serial reception enabled
0: Serial reception disabled
9^th Data Bit Transmitted In Modes 2 and 3.
This bit must be set by software and
cleared by software.
9^th Data Bit Received In Modes 2 and 3.
In Mode 1, if SM2=0, RB8 is the stop bit
that was received.
1
TI
0
RI
In Mode 0, this bit is not used.
This bit must be cleared by software.
Transmission Interrupt flag.
Automatically set to 1 when:
• The 8^th bit has been sent in Mode 0.
• Automatically set to 1 when the stop bit
has been sent in the other modes.
This bit must be cleared by software.
Reception interrupt flag automatically set to
1 when:
• The 8^th bit has been received in Mode 0.
• Automatically set to 1 when the stop bit
has been sent in the other modes (see
SM2 exception).
This bit must be cleared by software.
TABLE 22: SERIAL PORT MODES OF OPERATION
SM0
0
0
1
SM1
0
1
0
Mode
0
1
2
Description
Shift Register
8-bit UART
9-bit UART
1
1
3
9-bit UART
Baud Rate
Fosc/12
Variable
Fosc/64
or
Fosc/32
Variable
Modes of Operation
The VRS700’s serial port can operate in four different
modes. In all modes, a transmission is initiated by an
instruction that uses the SBUF SFR as a destination
register. In Mode 0, reception is initiated by setting RI
to 0 and REN to 1. An incoming start bit initiates
reception in the other modes provided that REN is set
to 1. The following sections describe the four modes.
Mode 0
In this mode (shown in Figure 15), serial data exits and
enters through the RXD pin. TXD is used to output the
shift clock. The signal is composed of 8 data bits
starting with the LSB. The baud rate in this mode is
1/12 the oscillator frequency.
FIGURE 15: SERIAL PORT MODE 0 BLOCK DIAGRAM
1
Write to
SB UF
Internal Bus
F osc/12
RI
REN
SQ
D
CLK
SB UF
Shift
ZERO DETECTOR
S tar t
TX Clock
Shift
TX Control Unit
TI
Send
Shift
Clock
Serial Port
Int errup t
RX Clock
RI
Receive
RX Control Unit
Start Shift 1 1 1 1 1 1 1 0
RXD P3.0
TXD P3.1
RXD P3.0
Input Function
Shift Register
RXD P3.0
SBUF
Internal Bus
READ SBUF
Transmission (Mode 0)
Any instruction that uses SBUF as a destination
register may initiate a transmission. The “write to
SBUF” signal also loads a 1 into the 9^th position of the
transmit shift register and tells the TX control block to
begin a transmission. The internal timing is such that
one full machine cycle will elapse between a write to
SBUF instruction and the activation of SEND. The
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