ACD82124 Datasheet, PDF (16/48 Pages) List of Unclassifed Manufacturers – 24 Ports 10/100 Fast Ethernet Switch Controller

7. REGISTER DESCRIPTION
Registers in the ACD82124 are used to define the op-
eration mode of various function modules of the switch
controller and the peripheral devices. Default values at
power-on are defined by the factory. The manage-
ment CPU (optional) can read the content of all regis-
ters and modify some of the registers to change the
operation mode. Table-7.0 lists all the registers inside
the switch controller.
Table-7.1: INTSRC Register
Bit
Description
0 System initialization completed
1
System error occurred
2
Port partition occurred
3
ARL Interrupt
4
Reserved
5
Reserved
6
Reserved
7
Reserved
Default
0
0
0
0
0
0
0
0
INTSRC register (register 1)
The INTSRC register indicates the source of the inter-
rupt request. Before the CPU starts to respond to an
interrupt request, it should read this register to find out
the interrupt source. This register is automatically
cleared after each read. Table-7.1 lists all the bits of
this register.
SYSERR register (register 2)
The SYSERR register indicates the presence of sys-
tem errors. It is automatically cleared after each read.
Table-7.2 lists all kind of system error.
Table-7.2: SYSERR Register
Bit
Description
0
BIST failure indication
1
Reserved
2
Reserved
3
Reserved
4
Reserved
5
Reserved
6
Reserved
7
Reserved
8
Reserved
Default
0
0
0
0
0
0
0
0
0
Table-7.0: Register List
Address
Name
0
1
INTSRC
2
SYSERR
3
PAR
4
PMERR
5
ACT
6-15
16
SYSCFG
17
INTMSK
18
SPEED
19
LINK
20
nFWD
21
nBP
22
nPORT
23
PVID
24
VPID
25
POSCFG
26
nPAUSE
27
DPLX
28
RVSMII
29
nPM
30
ERRMSK
31
CLKADJ
32-63
PHYREG
Type
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Size
8 Bit
24 Bit
24 Bit
24 Bit
24 Bit
16 Bit
8 Bit
24 Bit
24 Bit
24 Bit
24 Bit
24 Bit
4 Bit
5 Bit
19 Bit
24 Bit
24 Bit
5 Bit
24 Bit
8 Bit
4 Bit
16 Bit
Depth
Description
Reserved
1
Interrupt Source
1
System Error
1
Port Partition Indication
1
PHY Management Error
1
Port Avtivity
Reserved
1
System Configuration
1
Interrupt Mask
1
Port Speed
1
Port Link
1
Port Forward Disable
1
Port Back Pressure Disable
1
Port Disable
24
Port VLAN ID
4
VLAN Dumping Port
1
Power-On-Strobe Configuration
1
Port Pause Frame Disable
1
Port Duplex Mode
1
Reversed MII Selection
1
Port PHY Management Disable
1
Error Mask
1
ARL Clock Delay Adjustment
24
Registers in PHY device, (REG# - 32)
16