DM9161A Datasheet, PDF (15/45 Pages) List of Unclassifed Manufacturers – 10/100 MBPS FAST ETHEMET PHYSICAL LAYER SINGLE CHIP TRANSCEIVER

7.2 100Base-TX Operation
The 100Base-TX transmitter receives 4-bit nibble data
clocked in at 25MHz at the MII, and outputs a scrambled
5-bit encoded MLT-3 signal to the media at 100Mbps. The
on-chip clock circuit converts the 25MHz clock into a
125MHz clock for internal use.
The IEEE 802.3u specification defines the Media
Independent Interface. The interface specification defines
a dedicated receive data bus and a dedicated transmit
data bus.
These two busses include various controls and signal
indications that facilitate data transfers between the
DM9161A and the Reconciliation layer.
7.2.1 100Base-TX Transmit
The 100Base-TX transmitter consists of the functional
blocks shown in figure 7-3. The 100Base-TX transmit
section converts 4-bit synchronous data provided by the
MII to a scrambled MLT-3 125, a million symbols per
second serial data stream.
MII
Signals
25M OSCI
TX CGM
LED1-4#
LED
Driver
MII
Interface/
Control
4B/5B
Encoder
Scrambler
Parallel
to Serial
NRZ
to
NRZI
NRZI to
MLT-3
MLT-3
Driver
100TXD+/-
4B/5B
Decoder
Code-
group
Alignment
25M CLK
Rise/Fall
Time
CTL
125M CLK
"VUP.%*9
Descrambler
Serial to
Parallel
Digital
Logic
NRZI
to
NRZ
RX
CRM
MLT-3 to
NRZI
Adaptive
EQ
RXI+/-
10BASE-T ^RX
Module
TX
RXI+/-
10TXD+/-
Register
Collision
Detection
Carrier
Sense
Auto-
Negotiation
Figure 7-3
Preliminary
16
Version: DM9161A-DS-P04
Jan.19, 2005