TC2411 Datasheet, PDF (14/16 Pages) List of Unclassifed Manufacturers – 14-Bit, 1 GSPS Digital-to-Analog Converter with Standby Mode of Operation

Datasheet (Advance Information)
TC2411
Application Notes:
A. Power Supply Decoupling
Add power supply decoupling nearby package pins as summarized below:
1. AVEE – bypass each group of pins with 0.1 uF capacitor to AGND.
a. A12, B12
b. E1, F1, G1
c. H13, H14
2. DVEE – bypass each group of pins with 0.1 uF capacitor to DGND.
a. K1, K2, L1, L2
b. J14, K14
c. B5, B6
3. DVDD – bypass each group of pins with 0.1 uF capacitor to DGND.
a. B7, B8
b. L13
4. AVCC – bypass pin A2 with 0.1 uF capacitor to AGND.
5. DVCC – bypass pins A8, M2 and K13 with 1000 pF capacitor to DGND.
B. Analog Outputs (VOP, VON)
The TC2411 supplies differential analog DAC outputs at pins VOP and VON. Each pin is internally
terminated with 25 ohms to analog ground, creating an effective 50 ohm differential source. When these
outputs are connected to a single-ended, 50 ohm load through a 1:1 transformer, the resulting full-scale AC
swing is approximately 500 mVpp (20 mA into 25 ohms). Each DAC output may be dc-coupled to a ground-
referenced load.
C. Clock Inputs (CLKP, CLKN)
To achieve excellent phase noise performance, the TC2411 requires a differential clock input with low jitter
characteristics. A 2:1 transformer may be used to convert a single-ended, 50 ohm clock source and provide a
25 ohm, ac-coupled, differential drive into CLKP and CLKN. These inputs are internally biased and
terminated with 12.5 ohms per side.
A very low-phase noise (low jitter) sinewave clock signal should be used for enhanced SNR performance. A
sinewave oscillator featuring at least -130 dBc/Hz phase noise, above 20 KHz from the carrier is
recommended. Best noise performance is achieved with clock sources capable of 1.5 Vpp or greater outputs.
D. LVDS-Compliant Digital Inputs (D0P/N to D13P/N)
The TC2411 offers an LVDS-compliant interface into the 14 bit data inputs. These inputs are differentially
terminated on-chip with 100 ohms. 0000 corresponds to minus full-scale, while 3FFF represents plus full-
scale.
E. Reset/Burst Mode (RST)
The TC2411 offers a burst mode capability whereby the DAC analog output can be asynchronously reset to
the all zeros code (00 0000 0000 0000) irrespective of input data. Under normal operation, the RST pin
should be held high at +3.3V. When a low signal (0V) is applied to RST, the DAC output resets to the all
zeros code (minus full scale). Contact TelASIC sales for further information.
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MKDSTC2411 Rev-