HWD2111 Datasheet, PDF (13/19 Pages) List of Unclassifed Manufacturers – Dual 105mW Headphone Amplifier with Digital Volume Control and Shutdown Mode

Application Information (Continued)
Selection of Input and Output Capacitor Size
Besides gain, one of the major considerations is the closed
loop bandwidth of the amplifier. To a large extent, the band-
width is dicated by the choice of external components shown
in Figure 1. Both the input coupling capacitor, C_i, and the
output coupling capacitor, C_o, form first order high pass
filters which limit low frequency response. These values
should be based on the desired frequency response
weighed against the following:
Large value input and output capacitors are both expensive
and space consuming for portable designs. Clearly a certain
sized capacitor is needed to couple in low frequencies with-
out severe attenuation. But in many cases the speakers
used in portable systems, whether internal or external, have
little ability to reproduce signals below 150Hz. Thus large
input and output capacitors may not increase system perfor-
mance.
In addition to system cost and size, click and pop perfor-
mance is affected by the size of the input coupling capacitor,
C_i. A larger input coupling capacitor requires more charge to
reach its quiescent DC voltage (nominally 1/2 V_DD). This
charge comes from the output via the feedback and is apt to
create pops upon device enable. Turn on pops can be
minimized by reducing C_i value based on necessary low
frequency response.
Besides minimizing the input and output capacitor values,
careful consideration should be paid to the bypass capacitor
value. Bypass capacitor C_B is the most critical component to
minimize turn on pops since it determines how fast the
HWD2111 turns on. The slower the HWD2111’s outputs ramp to
their quiescent DC voltage (nominally 1/2 V_DD), the smaller
the turn on pop. While the device will function properly, (no
oscillations or motorboating), with C_B equal to 1µF, the de-
vice will be much more susceptible to turn on clicks and
pops. Thus, a value of C_B equal to 1µF or larger is recom-
mended in all but the most cost sensitive designs.
Also, careful consideration must be taken in selecting a
certain type of capacitor to be used in the system. Different
types of capacitors (tantalum, electrolytic, ceramic) have
unique performance characteristics and may affect overall
system performance.
Output Power vs Supply Voltage graphs in the Typical Per-
formance Characteristics section, the supply rail can be
easily found. A second way to determine the minimum sup-
ply rail is to calculate the required V_OPEAK using Equation (3)
and add the dropout voltage. For a single-ended application,
the minimum supply voltage can be approximated by
(2V_OPEAK + (V_ODTOP + V_ODBOT)), where V_ODBOT and V_ODTOP
are extrapolated from the Dropout Voltage vs Supply Voltage
curve in the Typical Performance Characteristics section.
(3)
Using the Output Power vs Supply Voltage graph for a 32Ω
load, the minimum supply rail is 4.8V. Since 5V is a standard
supply voltage in most applications, it is chosen for the
supply rail. Extra supply voltage creates headroom that al-
lows the HWD2111 to reproduce peaks in excess of 70mW
without clipping the signal. At this time, the designer must
make sure that the power supply choice along with the
output impedance does not violate the conditions explained
in the Power Dissipation section. Remember that the maxi-
mum power dissipation point from Equation 1 must be mul-
tiplied by two since there are two independent amplifiers
inside the package.
The final design step is to address the bandwidth require-
ments which must be stated as a pair of −3dB frequency
points. Five times away from a −3dB point is 0.17dB down
from passband response assuming a single pole roll-off. As
stated in the External Components section, C_i and C_o
create first order highpass filters. Thus to obtain the desired
frequency low response of 100Hz within ±0.5dB, both poles
must be taken into consideration. The combination of two
single order filters at the same frequency forms a second
order response. This results in a signal which is down
0.34dB at five times away from the single order filter −3dB
point. Thus, a frequency of 20Hz is used in the following
equations to ensure that the response is better than 0.5dB
down at 100Hz.
C_i ≥ 1 / (2π * 33 kΩ * 20 Hz) = 0.241µF; use 0.39µF. (4)
AUDIO POWER AMPLIFIER DESIGN
Design a Dual 70mW/32Ω Audio Amplifier
Given:
Power Output
Load Impedance
Input Level
Input Impedance
Bandwidth
70mW
32Ω
1Vrms (max)
33kΩ (min)
100 Hz–20 kHz ± 0.50dB
C_o ≥ 1 / (2π * 32Ω * 20 Hz) = 249µF; use 330µF. (5)
The high frequency pole is determined by the product of the
desired high frequency pole, f_H, and the closed-loop gain,
A_V. With a closed-loop gain of 3.98 or +12dB and f_H =
100kHz, the resulting GBWP = 398kHz which is much
smaller than the HWD2111 GBWP of 1MHz. This figure dis-
plays that at the maximum gain setting of 3.98 or +12dB, the
HWD2111 can be used without running into bandwidth
limitations.
A designer must first determine the minimum supply rail to
obtain the specified output power. By extrapolating from the
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