IS61LV6464 Datasheet, PDF (12/19 Pages) List of Unclassifed Manufacturers – 64K x 64 SYNCHRONOUS PIPELINE STATIC RAM

IS61LV6464
ISSI ^®
WRITE CYCLE TIMING
CLK
ADSP
ADSC
ADV
A15-A0
GW
BWE
BW8-BW1
CE
CE2, CE3
CE2, CE3
tKC
tKH
tKL
tSS
tSH
ADV must be inactive for ADSP Write ^tAVS
tAS
tAH
WR1
tWS
WR2
tWH
ADSP is blocked by CE inactive
ADSC initiate Write
tAVH
WR3
tWS
tWH
tWS
tWH
tWS
tWH
WR1
WR2
WR3
tCES
tCEH
CE Masks ADSP
tCES
tCEH
tCES
tCEH
CE3, CE2 and CE2, CE3 only sampled with ADSP or ADSC
Unselected with CE2, CE3
OE
DATAOUT
High-Z
tDS
tDH _{BW8-BW1 only are applied to first cycle of WR2}
DATAIN
High-Z
1a
2a
2b
2c
2d
3a
Single Write
Burst Write
Write
Unselected
12
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
01/15/04