FS6261-01 Datasheet, PDF (12/17 Pages) List of Unclassifed Manufacturers – Motherboard Clock Generator IC

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January 2000
Table 9: AC Timing Specifications, continued
Unless otherwise stated, all power supplies = 3.3V, no load on any output, and ambient temperature TA = 25°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and
are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical. Spread spectrum modulation is disabled except for Rise/Fall time measurements.
PARAMETER
SYMBOL
CONDITIONS/DESCRIPTION
133MHz
MIN. TYP. MAX.
100MHz
MIN. TYP. MAX.
UNITS
CPU_0:3 Clock Outputs (2.5V Type 1 Clock Buffer)
Duty Cycle *
dt
Ratio of high pulse width to one
clock period, measured at 1.5V
45
49
55
45
49
55
%
Clock Skew *
tskw
CPU to CPU @ 1.25V, CL=20pF
+60
+60
On rising edges 500µs apart at
Jitter, Long Term (σy(τ)) *
tj(LT)
1.25V relative to an ideal clock,
136
CL=20pF, all PLLs active
134
ps
Jitter, Period (peak-peak) *
tj(∆P)
From rising edge to rising edge at
1.25V, CL=20pF, all PLLs active
123
97
ps
Rise Time *
tr min
Measured @ 0.4V – 2.0V; CL=10pF
1.1
tr max
Measured @ 0.4V – 2.0V; CL=20pF
1.4
0.9
ns
1.4
Fall Time *
tf min
Measured @ 2.0V – 0.4V; CL=10pF
1.0
tf max
Measured @ 2.0V – 0.4V; CL=20pF
1.1
0.9
ns
1.2
Enable Delay *
tDLH
via CPU_STOP#
1.0
8.0 1.0
8.0
ns
Disable Delay *
tDHL
via CPU_STOP#
1.0
8.0 1.0
8.0
ns
REF_0:1 Clock Outputs (3.3V Type 3 Clock Buffer)
Duty Cycle *
dt
Ratio of high pulse width to one
clock period, measured at 1.5V
45
50
55
45
50
55
%
Jitter, Long Term (σy(τ)) *
On rising edges 500µs apart at 1.5V
tj(LT)
relative to an ideal clock, CL=20pF,
27
all PLLs active
23
ps
Jitter, Period (peak-peak) *
tj(∆P)
From rising edge to rising edge at
1.5V, CL=20pF, all PLLs active
177
111
ps
Rise Time *
tr min
Measured @ 0.4V – 2.4V; CL=10pF
0.9
tr max
Measured @ 0.4V – 2.4V; CL=20pF
1.4
0.9
ns
1.4
Fall Time *
tf min
Measured @ 2.4V – 0.4V; CL=10pF
1.0
tf max
Measured @ 2.4V – 0.4V; CL=20pF
1.6
1.0
ns
1.6
CK48 Clock Output (3.3V Type 3 Clock Buffer)
Duty Cycle *
Jitter, Long Term (σy(τ)) *
Jitter, Period (peak-peak) *
Rise Time *
Fall Time *
dt
Ratio of high pulse width to one
clock period, measured at 1.5V
45
51
55
45
51
55
%
On rising edges 500µs apart at 1.5V
tj(LT)
relative to an ideal clock, CL=20pF,
244
all PLLs active
246
ps
tj(∆P)
From rising edge to rising edge at
1.5V, CL=20pF, all PLLs active
143
202
ps
tr min
Measured @ 0.4V – 2.4V; CL=10pF
0.8
tr max
Measured @ 0.4V – 2.4V; CL=20pF
1.3
0.8
ns
1.3
tf min
Measured @ 2.4V – 0.4V; CL=10pF
0.9
tf max
Measured @ 2.4V – 0.4V; CL=20pF
1.4
0.9
ns
1.4
,62
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