AM79Q02 Datasheet, PDF (12/68 Pages) List of Unclassifed Manufacturers – Quad Subscriber Line Audio-Processing Circuit (QSLAC) Devices

ELECTRICAL CHARACTERISTICS
Typical values are for T_A = 25°C and nominal supply voltages. Minimum and maximum values are over the
temperature and supply voltage ranges shown in Operating Ranges.
Symbol
V_IL
V_IH
I_IL
V_OL
V_OH
I_OL
V_IR
V_IOS
Z_IN
I_IP
I_IN
Z_OUT
I_OUT
Z_REF
V_OR
V_OOS
V_OOSA
LIN_AISN
PD
C_I
C_O
PSRR
Parameter Descriptions
Input Low voltage
Input High voltage
Input leakage current
Output Low voltage
CD1–C5 (I_OL = 4 mA)
CD1–C5 (I_OL = 8 mA)
TSCA, TSCB (I_OL =14 mA)
Other digital outputs (I_OL = 2 mA)
Output High voltage
CD1–C5 (I_OH = 4 mA)
CD1–C5 (I_OH = 8 mA)
Other digital outputs (I_OH = 400 µA)
Output leakage current (H_I = Z state)
Analog input voltage range(AX = 0 dB)
(Relative to VREF)(AX = 6.02 dB)
Offset voltage allowed on VIN
Analog input impedance to VREF300 to 3400 Hz
Current into analog input for input voltages between
3.8 V and 5.0 V
Current out of analog input for input voltages between
0 V and 0.5 V
VOUT output impedance
VOUT output current (F< 3400 Hz)
VREF output impedance (F < 3400 Hz)
VOUT voltage range(AR = 0 dB)
(Relative to VREF)(AR = 6.02 dB)
VOUT offset voltage (AISN off)
VOUT offset voltage (AISN on)
Linearity of AISN circuitry (input = 0 dBm0)
Power dissipation
All channels active
1 channel active
All channels inactive, (in normal state)
All channels inactive (in low power state)
Input capacitance (Digital)
Output capacitance (Digital)
Power supply rejection ratio (1.02 kHz, 100 mV_RMS, ei-
ther path, GX = GR = 0 dB)
Min
2.0
–10
V_CCD – 0.4 V
V_CCD – 0.8 V
2.4
–10
–50
0.43
54
50
–4
70
–40
–80
–0.25
40
Typ
±1.584
±0.792
1
±1.584
±0.792
200
70
18
6
15
15
Max
0.8
+10
0.4
0.8
0.4
0.4
10
50
3.4
170
170
10
4
130
40
80
0.25
260
130
25
12
Unit Note
V
µA
1
V
1
µA
Vpk
mV
MΩ
2
µA
2
Ω
3
mApk
kΩ
Vpk
mV
4
LSB
mW
5
pF
dB
Notes:
1. The CD1, CD2, C3–C5 outputs are resistive for less than a 0.8 V drop. Total current must not exceed absolute maximum ratings.
2. When the digitizer saturates, a resistor of 50 kΩ ±20 kΩ is connected either to DGND or to VCCD — (1 diode drop) as
appropriate to discharge the coupling capacitor.
3. When the QSLAC device is in the Inactive state, the analog output will present either a VREF DC output level through a 15 kΩ
resistor (V_MODE = 0) or a high impedance (V_MODE = 1).
4. If there is an external DC path from VOUT to VIN with a gain of G_DC and the AISN has a gain of h_AISN, then the output offset
will be multiplied by 1/[1–(h_AISN • G_DC)].
5. Power dissipation in the Inactive state is measured with all digital inputs at V_IH = V_CC and V_IL = DGND and with no load
connected to VOUT₁, VOUT₂, VOUT₃, or VOUT₄.
12
Am79Q02/021/031 Data Sheet