SS1102C Datasheet, PDF (102/129 Pages) List of Unclassifed Manufacturers – Integrated MCU with Spread-Spectrum Transceiver (SST)

External Interrupts
before vectoring to any service routine. Condition 3 & 4 ensures that if the instruction in
progress is RETI or any access to IE or IP, then at least one more instruction will be
executed before any interrupt is vectored to.
The polling cycle is repeated with each machine cycle, and the values polled are the
values that were present at S5P2 of the previous machine cycle. Note then that if an
interrupt flag is active but not being responded to for one of the above conditions, if the
flag is not still active when the blocking condition is removed, the denied interrupt will
not be serviced. In other words, the fact that the interrupt flag once active but not
serviced is not remembered. Every polling cycle is new.
The processor acknowledges an interrupt request by executing a hardware generated
LCALL to the appropriate service routine. It also clears the flag that generated the
interrupt. The hardware generated LCALL pushes the contents of the Program Counter
onto the stack (but it does not save the PSW) and reloads the PC with an address that
depends on the source of the interrupt being vectored to.
Executing proceeds from that location until the RETI instructions is encountered. The
RETI instruction informs the processor that this interrupt routine is no longer in
progress, then pops the top two bytes from the stack and reloads the Program Counter.
Execution of the interrupted program continues from where it left off. Note that a simple
RET instruction would also have returned execution to the interrupted program, but it
would have left the interrupt control system thinking an interrupt was still in progress.
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