NRF402 Datasheet, PDF (10/16 Pages) List of Unclassifed Manufacturers – 433MHz Single Chip RF Transmitter

PRODUCT SPECIFICATION
nRF402 Single Chip RF Transmitter
Power up
PWR_UP is a digital input for selection of normal operating mode or standby mode.
PWR_UP = “1” selects normal operating mode.
PWR_UP = “0” selects standby mode.
LPF pin
LPF is the loop filter test pin. This may be used for measurement of the loop filter
voltage. In a normal application this pin should only be connected to a solder pad. No
PCB lines should be connected to this pin.
Frequency difference between transmitter and receiver
Assuming the nRF401 transceiver chip is used for demodulation, the total frequency
difference between transmitter and receiver should not exceed 70 ppm (30 kHz). This
yields a crystal stability requirement of ±35 ppm for the transmitter and receiver.
Frequency difference exceeding this will result in a 12dB/octave drop in receiver
sensitivity. The functional window of the transmission link is typically 450 ppm (200
kHz).
Example: A crystal with ±20 ppm frequency tolerance and ±25 ppm frequency
stability over temperature has a worst case frequency difference of ±45 ppm. If the
transmitter and receiver operate in different temperature environments, the resulting
worst-case frequency difference may be as high as 90 ppm. Resulting drop in
sensitivity due to the extra 20 ppm, is then approx. 5dB.
PCB layout and decoupling guidelines
A well-designed PCB is necessary to achieve good RF performance. A PCB with a
minimum of two layers including a ground plane is recommended for optimum
performance.
The nRF402 DC supply voltage should be decoupled as close as possible to the VDD
pins with high performance RF capacitors, see Table 8. It is preferable to mount a
large surface mount capacitor (e.g. 2.2 µF ceramic) in parallel with the smaller value
capacitors. The nRF402 supply voltage should be filtered and routed separately from
the supply voltages of any digital circuitry.
Long power supply lines on the PCB should be avoided. All device grounds, VDD
connections and VDD bypass capacitors must be connected as close as possible to the
nRF402 IC. For a PCB with a topside RF ground plane, the VSS pins should be
connected directly to the ground plane. For a PCB with a bottom ground plane, the
best technique is to have via holes in or close to the VSS pads.
Full swing digital data or control signals should not be routed close to the external
VCO inductor or the LPF pin.
The VCO inductor placement is important. The optimum placement of the VCO
inductor gives a PLL loop filter voltage of 1.1 ±0.2 V, which can be measured at LPF
(pin 6). For a 22nH, 0603 size inductor the length between the centre of the
Nordic VLSI ASA
Revision: 2.1
Vestre Rosten 81, N-7075 Tiller, Norway -
Page 10 of 16
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February 2000