MU9C1480A Datasheet, PDF (10/28 Pages) List of Unclassifed Manufacturers – The 1024 x 64-bit LANCAM facilitates numerous 1024 x 64-bit CMOS content-addressable memory (CAM)

MU9C1480A/L Draft
OPERATIONAL CHARACTERISTICS Continued
Cycle Type /E /CM /W I/O Status SPS SPD TCO Operation
Notes
Cmd Write L L L
IN
Load Instruction decoder
1
IN
ü ^{Load Address register}
2,3
IN
ü ^{Load Control register}
3
IN
ü ^{Load Page Address register}
3
IN
ü ^{Load Segment Control register}
3
IN
ü ^{Load Device Select register}
3
IN
Deselected
10
Cmd Read L L H
OUT
ü ^{Read Next Free Address register}
3
OUT
ü ^{Read Address register}
3
OUT
Read Status Register bits 15–0
4
OUT
Read Status Register bits 31–16
5
OUT
OUT
OUT
OUT
OUT
HIGH-Z
ü ^{Read Control register}
3
ü ^{Read Page Address register}
3
ü ^{Read Segment Control register}
3
ü ^{Read Device Select register}
3
ü ^{Read Current Persistent Source or Destination 3,11}
Deselected
10
Data Write L H L
IN
ü
Load Comparand register
6,9
IN
ü
Load Mask Register 1
7,9
IN
ü
Load Mask Register 2
7,9
IN
ü
Write Memory Array at address
7,9
IN
ü
Write Memory Array at Next Free address
7,9
IN
ü
Write Memory Array at Highest-Priority match
7,9
IN
Deselected
10
Data Read L H H
OUT
ü
Read Comparand register
6, 9
OUT
ü
Read Mask Register 1
8, 9
OUT
ü
Read Mask Register 2
8, 9
OUT
ü
Read Memory Array at address
8, 9
OUT
ü
Read Memory Array at Highest-Priority match 7, 8
HIGH-Z
Deselected
10
H X X _HIGH-Z
Deselected
Notes:
1. Default Command Write cycle destination (does not require a TCO instruction).
2. Default Command Write cycle destination (no TCO instruction required) if Address Field flag was set in bit 11 of the
instruction loaded in the previous cycle.
3. Loaded or read on the Command Write or Read cycle immediately following a TCO instruction. Active for one Command
Write or Read cycle only. NFA register cannot be loaded this way.
4. Default Command Read cycle source (does not require a TCO instruction).
5. Default Command Read cycle source (does not require a TCO instruction) if the previous cycle was a Command Read of
Status Register Bits 15–0. If next cycle is not a Command Read cycle, any subsequent Command Read cycle will access the
Status Register Bits 15–0.
6. Default persistent source and destination on power-up and after Reset. If other resources were sources or destinations,
SPD CR or SPS CR restores the Comparand register as the destination or source.
7. Selected by executing a Select Persistent Destination instruction.
8. Selected by executing a Select Persistent Source instruction.
9. Access may require multiple 16-bit Read or Write cycles. The Segment Control register is used to control the selection of the
desired 16-bit segment(s) by establishing the Segment counters’ start and end limits and count values.
10. Device is deselected if Device Select register setting does not equal Page Address register setting, unless the Device Select
Register is set to FFFFH, which allows only write access to the device. (Writes to the Device Select register are always
active.) Device may also be deselected under locked daisy chain conditions as shown in Tables 5a and 5b on page 12.
11. A Command Read cycle after a TCO PS or TCO PD reads back the Instruction decoder bits that were last set to select a
persistent source or destination. The TCO PS instruction will also read back the Device ID.
Table 3: Input/Output Operations
Rev. 3.0 Draft
10