F29C51001 Datasheet, PDF (10/16 Pages) List of Unclassifed Manufacturers – 1MEGABIT(131,072 x 8 BIT) 5 VOLT CMOS FLASH MEMORY

SyncMOS
F29C51001T/F29C51001B
Decoding Mode
CE
OE
WE
A₀
A₁
A₉
I/O
Disabling Boot Block Protection Lock
V_H
V_H
V_IL
X
X
V_H
X
Output Disable
V_IL
V_IH
V_IH
X
X
X
HIGH-Z
NOTES:
1. X = Don’t Care, V_IH = HIGH, V_IL = LOW. V_H = 12.5V Max.
2. PD: The data at the byte address to be programmed.
Table 2. Command Codes
Command
Sequence
First Bus
Second Bus
Third Bus
Fourth Bus
Program Cycle Program Cycle Program Cycle Program Cycle
Address Data Address Data Address Data Address Data
Fifth Bus
Six Bus
Program Cycle Program Cycle
Address Data Address Data
Read
XXXXH F0H
Read
5555H AAH 2AAAH 55H 5555H F0H RA
RD
Autoselect
5555H
AAH 2AAAH 55H 5555H
90H 00H
01H
40H
01H⁽¹⁾
A1H⁽²⁾
Byte
Program
5555H AAH 2AAAH 55H 5555H A0H PA
PD(4)
Chip Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H
Sector Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H PA(3)
30H
NOTES:
1. Top Boot Sector
2. Bottom Boot Sector
3. PA: The address of the memory location to be programmed.
4. PD: The data at the byte address to be programmed.
Chip Erase Cycle
The F29C51001T/F29C51001B features a chip-
erase operation. The chip erase operation is
initiated by using a specific six-bus-cycle
sequence: two unlock program cycles, a setup
command, two additional unlock program cycles,
and the chip erase command (see Table 2).
The chip erase operation is performed
sequentially, one sector at a time. When the
automated on chip erase algorithm is requested
with the chip erase command sequence, the device
automatically programs and verifies the entire
memory array for an all zero pattern prior to erasure
The automatic erase begins on the rising edge of
the last WE or CE pulse in the command sequence
and terminates when the data on DQ7 is “1”.
Program Cycle Status Detection
There are two methods for determining the state
of the F29C51001T/F29C51001B during a
program (erase/program) cycle: DATA Polling
(I/O₇) and Toggle Bit (I/O₆).
DATA Polling (I/O₇)
The F29C51001T/F29C51001B features DATA
polling to indicate the end of a program cycle.
When the device is in the program cycle, any
attempt to read the device will received the
complement of the loaded data on I/O₇. Once the
program cycle is completed, I/O₇ will show true
data, and the device is then ready for the next
cycle.
Toggle Bit (I/O₆)
The F29C51001T/F29C51001B also features
another method for determining the end of a
program cycle. When the device is in the program
cycle, any attempt to read the device will result in
l/O₆ toggling between 1 and 0. Once the program is
completed, the toggling will stop. The device is then
ready for the next operation. Examining the toggle
bit may begin at any time during a program cycle.
F29C51001T/F29C51001B V1.0 May 1999
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