DEM16217SYH Datasheet, PDF (10/21 Pages) List of Unclassifed Manufacturers – Display Elektronik GmbH

DEM 16217 SYH
Product specification
7).Set CGRAM Address
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 1 AC5 AC4 AC3 AC2 AC1 AC0
Set CGRAM Address to AC .
This instruction makes CGRAM data available from MPU.
8).Set DDRAM Address
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 1 AC6 AC5 AC4 AC3 AC2 AC1 AC0
Set DDRAM Address to AC .
This instruction makes DDRAM data available from MPU.
In 1-line display mode (N=0 ), DDRAM address is from "00H" to "4FH".
In 2-line display mode (N=1 ), DDRAM address in the 1st line is from "00H" to "27H",and DDRAM address in
the 2nd line is from "40H" to "67H".
9) Read Busy Flag & Address
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 BF AC6 AC5 AC4 AC3 AC2 AC1 AC0
This instruction shows whether KS0070B is in internal operation or not. If the resultant BF is High, the internal opera-
ation is in progress and should wait until BF to become "Low", which by then the next instruction can be performed.
In this instruction value of address counter can also be read.
10) Write data to RAM
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1 0 D7 D6 D5 D4 D3 D2 D1 D0
Write binary 8-bit data to DDRAM/CGRAM.
The selection of RAM from DDRAM, CGRAM , is set by the previous address set instruction: DDRAM
address set, CGRAM address set, RAM set instruction can also determines the AC direction to RAM.
After write operation, the address is automatically increased/decreased by 1, according to the entry mode.
11) Read data from RAM
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1 1 D7 D6 D5 D4 D3 D2 D1 D0
Read binary 8-bit data from DDRAM/CGRAM .
The selection of RAM is set by the previous address set instruction. If address set instruction of RAM is not
performed before this instruction, the data that is read first is invalid, as the direction of AC is not determined. If the
RAM data is read several times without RAM address set instruction before read operation, the correct RAM data
from the second, but the first data would be incorrect, as there is no time to transfer RAM data. In case of DDRAM
read operation, cursor shift instruction plays the same role as DDRAM address set instruction: it also transfer RAM
data to output data register.
After read operation address counter is automatically increased/decreased by 1 according to the entry mode.
After CGRAM read operation, display shift may not be executed correctly.
*In the case of RAM write operation, AC is increased/decreased by 1 like read operation after this. In this time, AC
indicates the next address position, but onlythe previous data can be read by read instruction.
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