V292BMC Datasheet, PDF (1/14 Pages) List of Unclassifed Manufacturers – HIGH PERFORMANCE BURST DRAM CONTROLLER FOR Am29030/40 PROCESSORS

V292BMC Rev. D
HIGH PERFORMANCE BURST
DRAM CONTROLLER
FOR Am29030/40 PROCESSORS
• Pin/Software compatible with earlier V292BMC.
• Direct interfaces to Am29030/40 processors.
• 3.3V DRAM interface support.
• Near SRAM performance achieved with DRAM.
• Supports up to 512Mb of DRAM.
• Interleaved or non-interleaved operation.
• Supports symmetric and non-symmetric arrays.
The V292BMC Revision D Burst DRAM
Controller is an enhanced version of the previous
V292BMC with improved timing and provides
dedicated Power and Ground rails to support the
increasingly popular 3.3V DRAM modules.
Timing parameters are also improved over the
older versions of the device.
The V292BMC provides the DRAM access
protocols, buffer signals, data multiplexer
signals, and bus timing resources required to
work with DRAM. By using the V2926BMC,
system designers can replace tedious design
work, expensive FPGAs and valuable board
space with a single, high-performance, easily
configured device. The processor interface of the
V292BMC implements the bus protocol of the
Am29030/40. The pin naming convention has
been duplicated on the V292BMC; simply wire
like-named pins together to create the interface.
The V292BMC supports a total DRAM memory
subsystem size of 512Mbytes. The array may be
• Software-configured operational parameters.
• Integrated Page Cache Management.
• 2Kbyte burst transaction support.
• On chip memory address multiplexer/drivers.
• Two 24-bit timers, 8-bit bus watch timer.
• Up to 40MHz operation.
• Low cost 132-pin PQFP package.
organized as 1 or 2 leafs of 32-bits each.
Standard memory sizes of 256Kbit to 64Mbit
devices are supported and 8, 16, and 32-bit
accesses are allowed. The V292BMC takes
advantage of Fast Page Mode or EDO DRAMs
and row comparison logic to achieve static RAM
performance using dynamic RAMs. Control
signals required for optional external data path
buffers/latches are also provided by the
V292BMC. The V292BMC provides an 8-bit bus
watch timer to detect and recover from accesses
to unpopulated memory regions.Two 24-bit
counters/timers can supply an external interrupt
signal at a constant frequency relative to the
system clock. The V292BMC is packaged in a
low-cost 132-pin PQFP package and is available
in 25, 33, or 40MHz versions.
This document contains the product codes,
pinouts, package mechanical information, DC
characteristics, and AC characteristics for the
V292BMC. Detailed functional information is
contained in the User’s Manual.
Am29030/40
CPU
V292BMC
MEMORY
CONTROL
D
R
ROM
A
M
VxxxEPC
LOCAL TO
PCI BRIDGE
PCI
PERIPHERAL
TYPICAL APPLICATION
PCI SLOT or EDGE CONNECTOR
Copyright © 1998, V3 Semiconductor Corp.
V292BMC Data Sheet Rev 3.2X
1
V3 Semiconductor reserves the right to change the specifications of this product without notice.
V292BMC is trademark of V3 Semiconductor. All other trademarks are the property of their respective owners.