UD61256 Datasheet, PDF (1/13 Pages) Zentrum Mikroelektronik Dresden AG – 256K x 1 DRAM

Maintenance only
UD61256
256K x 1 DRAM
Features
Description
Data Output Control
F Dynamic random access memory Addressing
The usual state of the data output is
the High-Z state. Whenever CAS is
262144 x 1 bit manufactured
The UD61256 is a dynamic Write- inactive (HIGH), Q will float (High-Z).
using a CMOS technology
F RAS access times 70 ns, 80 ns
F TTL-compatible
F Three-state output
F 256 refresh cycles
Read-memory with random access. Thus, CAS functions as data output
FPM facilitates faster data operation control.
with predefined row address. Via 9 After access time, in case of a Read
address inputs the 18 address bits cycle, the output is activated, and it
are transmitted into the internal contains the logic „0“ or „1“.
4 ms refresh cycle time
F FAST PAGE MODE
F Operating modes: Read, Write,
address memories in a time-multi- Q is then valid until CAS returns into
plex operation. The falling RAS- to inactive state (HIGH).
edge takes over the row address. The memory cycle being a Read,
Read - Write,
During RAS Low, the column Read-Write or a Write cycle (W-con-
RAS only Refresh,
address together with the CAS trolled), Q changes from High-Z
Hidden Refresh with address
signal are taken over. The selection state to the active state („0“ or „1“).
transfer
F Power Supply Voltage 5 V
F Packages PDIP16 (300 mil)
of one or more memory circuits can After the access time the contents of
be made by activation of the RAS the selected cell is available, except
input.
for the Write cycle.
F ^{SOJ20/26 (300 mil)}
Operating temperature range
Read-Write-Control
The output remains active until CAS
becomes inactive, irrespective of
F ^{0 to 70 °C}
The choice between Read or Write RAS becoming inactive or not. The
Quality assessment according to cycle is made at the W input. HIGH memory cycle being a Write cycle
CECC 90000, CECC 90100 and at the W input causes a Read cycle, (CAS-controlled), the data output
CECC 90112
meanwhile LOW leads to a Write keeps its High-Z state throughout
cycle.
the whole cycle. This configuration
Both CAS-controlled and W-control- makes Q fully controllable by the
led Write cycles are possible with user merely through the timing of W.
activated RAS signal.
The output storaging the data, they
remain valid from the end of access
time until the start of another cycle.
Pin Configuration
Pin Description
A8
D
W
RAS
n.c.
n.c.
A0
A2
A1
VCC
1
26
2
25
3
24
4
23
5
22
SOJ
9
18
10
17
11
16
12
15
13
14
V
CAS
Q
A6
n.c.
A8
D
W
RAS
A0
A2
A1
VCC
n.c.
A3
A4
A5
A7
1
16
2
15
3
14
4
13
PDIP
5
12
6
11
7
10
8
9
Top View
VSS
CAS
Q
A6
A3
A4
A5
A7
Top View
December 12, 1997
1
Signal Name
A0 - A8
D
W
RAS
UCC
USS
CAS
Q
n.c.
Signal Description
Address Inputs
Data Input
Read, Write Control
Row Address Strobe
Power Supply Voltage
Ground
Column Address Strobe
Data Output
no connected