SY10422-3 Datasheet, PDF (1/10 Pages) List of Unclassifed Manufacturers – 256 x 4 ECL RAM

SY NERGY
SEMICONDUCTOR
256 x 4 ECL RAM
SY10422-3/4/5/7
SY10^SS4^YY2¹¹2⁰⁰-⁰¹3⁴⁴²²/4^22--/³³5^///⁴⁴7^//55//77
SY100422-3/4/5/7
SY101422-3/4/5/7
FEATURES
s Address access time, tAA: 3/4/5/7ns max.
s Block select access time, tAB: 2ns max.
s Write pulse width, tWW: 3ns min.
s Edge rate, tr/tf: 500ps typ.
s Write recovery times under 5ns
s Power supply current, IEE: –250mA, –200mA
for –5/7ns
s Superior immunity against alpha particles provides
virtually no soft error sensitivity
s Built with advanced ASSET™ technology
s Fully compatible with industry standard 10K/100K
ECL I/O levels
s Noise margins improved with on-chip voltage and
temperature compensation
s Open emitter output for easy memory expansion
s Includes popular Block Select function allowing
individual read/write control over blocks
s ESD protection of 2000V
s Available in 24-pin flatpack and 28-pin PLCC and
MLCC packages
DESCRIPTION
The Synergy SY10/100/101422 are 1024-bit Random
Access Memories (RAMs), designed with advanced Emitter
Coupled Logic (ECL) circuitry. The devices are organized
as 256-words-by-4-bits and meet the standard 10K/100K
family signal levels. The SY100422 is also supply voltage-
compatible with 100K ECL, while the SY101422 operates
from 10K ECL supply voltage (–5.2V). All feature on-chip
voltage and temperature compensation for improved noise
margin.
The SY10/100/101422 employ proprietary circuit design
techniques and Synergy’s proprietary ASSET advanced
bipolar technology to achieve extremely fast access, write
pulse width and write recovery times. ASSET uses
proprietary technology concepts to achieve significant
reduction in parasitic capacitance while improving device
packing density. Synergy’s circuit design techniques, coupled
with ASSET, result not only in ultra-fast performance, but
also allow device operation at reduced power levels with
virtually no soft error sensitivity and with outstanding device
reliability in volume production.
BLOCK DIAGRAM
A0
A5
A6
A7
Y-Decoder/Driver
A1
A2
Memory Cell Array
A3
A4
© 1999 Micrel-Synergy
WE
SA/WA* SA/WA SA/WA SA/WA
DI0
DI1
DI2
DI3
BS0
BS1
BS2
BS3
DO0
DO1
DO2
DO3
* SA = Sense Amplifier
WA = Write Amplifier
1
Rev.: E Amendment: /0
Issue Date: August,1999