STK16C88-3 Datasheet, PDF(1/11 Page) List of Unclassifed Manufacturers – 32K x 8 AutoStorePlus nvSRAM 3.3V QuantumTrap CMOS Nonvolatile Static RAM

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STK16C88-3 Datasheet, PDF (1/11 Pages) List of Unclassifed Manufacturers – 32K x 8 AutoStorePlus nvSRAM 3.3V QuantumTrap CMOS Nonvolatile Static RAM

STK16C88-3

32K x 8 AutoStorePlusâ¢ nvSRAM

3.3V QuantumTrapâ¢ CMOS

Nonvolatile Static RAM

FEATURES

â¢ Transparent Data Save on Power Down

â¢ Internal Capacitor Guarantees AutoStoreâ¢

Regardless of Power-Down Slew Rate

â¢ Directly Replaces 32K x 8 Static RAM, Battery-

Backed RAM or EEPROM

â¢ 35 Access Time

â¢ STORE to Nonvolatile Elements Initiated by

Software or AutoStorePlusâ¢

â¢ RECALL to SRAM Initiated by Software or

Power Restore

â¢ 10mA Typical ICC at 200ns Cycle Time

â¢ Unlimited READ, WRITE and RECALL Cycles

â¢ 1,000,000 STORE Cycles to Nonvolatile Ele-

ments (Commercial/Industrial)

â¢ 100-Year Data Retention in nonvolatile ele-

ments (Commercial/Industrial)

â¢ Single 3.3V + 0.3V Operation

â¢ Commercial and Industrial Temperatures

â¢ 28-Pin PDIP Package

DESCRIPTION

The STK16C88-3 is a fast SRAM with a nonvolatile

element incorporated in each static memory cell.

The SRAM can be read and written an unlimited

number of times, while independent nonvolatile data

resides in Nonvolatile Elements. Data transfers from

the SRAM to the Nonvolatile Elements (the STORE

operation) can take place automatically on power

down. An internal capacitor guarantees the STORE

operation regardless of power-down slew rate.

Transfers from the Nonvolatile Elements to the

SRAM (the RECALL operation) take place automati-

cally on restoration of power. Initiation of STORE and

RECALL cycles can also be controlled by entering

control sequences on the SRAM inputs. The

STK16C88-3 is pin-compatible with 32k x 8 SRAMs

and battery-backed SRAMs, allowing direct substitu-

tion while providing superior performance. The

STK14C88-3, which uses an external capacitor, is

also available.

BLOCK DIAGRAM

A11

A12

A13

A14

QUANTUM TRAP

512 x 512

STATIC RAM

ARRAY

512 x 512

STORE

RECALL

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

COLUMN I/O

COLUMN DEC

A0 A1 A2 A3 A4A10

STORE/

RECALL

CONTROL

VCC

POWER

CONTROL

INTERNAL

CAPACITOR

PIN CONFIGURATIONS

A14 1

A12 2

A7 3

A6 4

A5 5

A4 6

A3 7

A2 8

A1 9

A0 10

DQ0 11

DQ1 12

DQ2 13

VSS 14

28 VCC

27 W

26 A13

25 A8

24 A9

23 A11

22 G

21 A10

20 E

19 DQ7

18 DQ6

17 DQ5 28 - 600 PDIP

16 DQ4

15 DQ3

SOFTWARE

DETECT

A0 - A13

PIN NAMES

A0 - A14

Address Inputs

Write Enable

DQ0 - DQ7

Data In/Out

Chip Enable

Output Enable

VCC

Power (+ 3.3V)

VSS

Ground

March 2006

1 Document Control # ML0019 rev 0.2

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